Mirabilis Design Inc.
Sunnyvale, CA 94087 [email protected]
Architecture exploration has been the holy grail of product design. It has the potential to completely transform product engineering. Research and use cases evaluations have shown that 80% of system optimization and almost 100% of the performance/power trade-offs can be achieved during architecture exploration.
In Part 1 of this two-part series we addressed the need for early-stage power analysis in complex SoCs and system designs, and introduced the VisualSim graphical modeling tool as a comprehensive energy simulation solution. In Part 2, we show how VisualSim performs when forecasting and expressing power values across several scenarios (offset concurrent tasks; comparing a single core at 1 GHz to four cores at 250 MHz; dynamic voltage frequency scaling (DVFS); and power gating) in a multicore embedded environment.
With the increase in SoC design complexity, system-level power estimation is becoming a critical factor. Part one of this two-part series explains why this is the case and introduces a comprehensive modeling platform for evaluating the power consumption of subsystems, chips, and entire systems.
The company claims that its 2 nm research chip’s “tiniest components are smaller than a strand of DNA.”
The pandemic sweeping the world, COVID-19, has rendered a large proportion of the workforce unable to commute to work, as to mitigate the spread of the virus.
Architecture exploration of AI applications is complex and involves multiple studies. To start with, we can target a single problem such as memory access or can look at the full processor or system.