IBM's 2 nm Transistor Breakthrough Puts Chip Design Under the Microscope
June 18, 2021
The company claims that its 2 nm research chip’s “tiniest components are smaller than a strand of DNA.”
There is continually increasing demand for superior chip performance and energy efficiency, especially in the era of thte hybrid cloud, AI, and IoT. IBM's new breakthrough transistor technology, 2 nm chips, helps address this growing demand.
The company claims that its 2 nm research chip’s “tiniest components are smaller than a strand of DNA.” IBM's industry-first nanosheet technology permits the advanced scaling of the 2 nm architecture, which leverages an increased number of transistors per chip that allow for smaller, faster, more reliable, and more efficient devices – they are projected to achieve 45 percent higher performance or use 75 percent less energy than today's most advanced 7 nm node chips.
This 2 nm breakthrough will cram up to 50 billion transistors on a chip the size of a fingernail.
Beyond FinFETs and 7 nm
As TSMC changes to 5 nm transistor designs and Intel struggles for 7 nm, IBM's 2-nm node chip tops them all. The company's $3 billion "Seven Nanometers and Beyond" research program is venturing outside of traditional FinFET designs, which worked well when 22 nm was the norm but struggle with the ridiculous scales of today’s chips. New nanosheet designs, mentioned previously, are part of a "gate-all-around" design paradigm that relieves the challenges of us FinFETs' leaky currents.
IBM has one of the world’s leading research centers on future semiconductor technology in Albany, New York, where it works closely with Rensselaer Polytechnic Institute, a school comparable to MIT when it comes to STEM programs.
If you're looking for an answer to the question of when we can expect to start seeing these, IBM announced its milestone 5 nm design within 4 years of development. It's also important to note that Intel is collaborating with IBM on their 2 nm process-point nano-sheet methodology. So, expect everyone from Intel to TSMC to be at 2 nm in about five years, at which point transistors will be about the size of an atom.
Process Node Advances Put Chip Designers Under the Microscope
With the continued increase in the number of transistors on a chip, processor designers will have more opportunities to infuse core-level innovations that improve capabilities for leading edge workloads like AI and cloud computing, as well as new pathways for hardware-enforced security and encryption. IBM is already implementing other innovative core-level enhancements in the latest generations of IBM hardware, like IBM POWER10 and IBM z15.
But with smaller transistors, inefficiency can creep into the design processes as the architects have more gates on which to deliver their applications. System-Level Design and Architecture Exploration can ensure that under- and over-design are avoided by running extensive workloads and use-cases on the proposed design – this ensures that you do not go overboard with clocking. System modeling software, such as Ptolemy from UC Berkeley and VisualSim Architect from Mirabilis Design, have large libraries of system components that make modeling easy and quick, thus delivering intelligent diagnostics for the efficiency challenge. To manage the vast amount of data, VisualSim's Processor Generator leverages AI to conduct performance analysis and architecture exploration of SoCs and embedded systems based on these advanced technologies.
There are many potential benefits of these advanced 2 nm chips. Cell phone battery life can be quadrupled, allowing users to charge their devices every four days; Laptop and PC functions will realize a drastic speed-up in functions like application processing; Language translation will happen more easily; Internet access will be faster internet access; Object detection and reaction times in autonomous vehicles will be quicker; and more.
Prepare to work under the microscope.