Henderson, Nevada. Aldec, renovated its linting tool ALINT-PRO to increase the support of Microchip Technology's Libero SoC Design Suite. The update allows for automatic conversion of Libero projects into ALINT-PRO’s ecosystem for static linting and clock domain crossing (CDC) evaluation of hardware devices in VHDL, Verilog, or SystemVerilog.

TySOM boards can be used either as the main edge processing device or as a gateway to AWS.

Aldec now offers the complete and customizable qualification package for the Basic Tool Qualification process.

Aldec has added VHDL-2019 feature support and a UVM Registers window to Riviera-PRO, the company's simulation and debugging tool.

The 2020.3 release of Aldec's Spec-TRACER bridges the communication gap between system and hardware development teams by adding integration with IBM Requirements Engineering DOORS Next.

By integrating Aldec?s Riviera-PRO? with Codasip?s Studio?, verification of custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment.

Riviera-PRO 2019.10 is now available for download and evaluation.