Aldec Enhances Riviera-PRO's VHDL and UVVM Support

By Tiera Oliver

Associate Editor

Embedded Computing Design

December 19, 2019

News

Aldec Enhances Riviera-PRO's VHDL and UVVM Support

Riviera-PRO 2019.10 is now available for download and evaluation.

Aldec, a company specializing in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).

Users interested in benefiting from the latest developments in the VHDL standard, i.e. VHDL 1076-2018, can now use Riviera-PRO 2019.10 to access newer attributes and improvements of existing implementations of VHDL-2018, like the to_string function and 'IMAGE attribute can be applied to all composite types that are representable.

As for the 2019.09.02 release of UVVM, the open source architecture, library, and methodology for creating VHDL testbenches, its updates include new config to deassert tvalid once or multiple random times in AXI-Stream BFM and the new feature to deassert tready multiple random times in AXI-Stream BFM.

In addition, Riviera-PRO's Register Generator has been enhanced to support FIFOs, indirect registers and arrays of registers.

Riviera-PRO 2019.10 is now available for download and evaluation.

For more information, please visit: www.aldec.com

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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