Xilinx-Compliant Design IP Accessible to Xilinx Customers through Partner Program
SmartDV Technologies announced support of the ARINC standards with its Design and Verification IP.
SmartDV has packaged the SmartViP Debug, a tool designed for automated protocol debugging, and SmartTestBench, which automatically generates testbench files and includes a variety of verification scenarios, into a unified automation tool suite. By identifying protocol violations and presenting them in graphical views or through tabular or text-based representations, the combined offering helps eliminate manual verification processes.
SmartDV Technologies and Aldec inked an agreement linking SmartDV's Verification IP with Aldec's Riviera-PRO high-performance simulation and debugging tool.