SmartDV Automation Tool Suite Accelerates Protocol Debug, Testbench Creation
May 17, 2021
SmartDV has packaged the SmartViP Debug, a tool designed for automated protocol debugging, and SmartTestBench, which automatically generates testbench files and includes a variety of verification scenarios, into a unified automation tool suite. By identifying protocol violations and presenting them in graphical views or through tabular or text-based representations, the combined offering helps eliminate manual verification processes.
SmartViP supports simulation, emulation, and SystemC verification environments, and leverages a profile-based architecture that’s compatible with industry-standard protocols. It can be applied to all industry standard waveform viewers, where protocol violations are displayed in waveform view alongside proper protocol behavior.
SmartTestBench automates the creation of testbench files to support:
- Assertion IP for Formal Property Verification
- Post-silicon verification
- System Verilog and System C
- SystemC and transaction-level modeling (TLM)
- Synthesizable emulators and FPGA prototypes
- UVM and OVM verification IP
- And others
With SmartTestBench, users can select protocols and IP types from a GUI and configure the test bench to match that configuration. It also supports text file inputs and connects to SmartViP Debug to enable visual debugging during testbench creation.
The automation suite is available now to SmartDV Verification IP customers for free. For more information visit Smart-DV.com.