Fraunhofer IPMS, CAST to Launch a New Processor IP for Edge AI Applications

By Abhishek Jadhav

Freelance Tech Writer

December 09, 2021

Blog

Fraunhofer IPMS, CAST to Launch a New Processor IP for Edge AI Applications

All the technological advancements in developing efficient processor cores have led several semiconductor players to design processor IP using open-source instruction set architecture.

To meet increasing demands for energy efficiency and high performance in Edge AI, Fraunhofer IPMS and CAST have jointly announced an embedded processor based on the open standard RISC-V ISA. 

This comes as an upgrade to CAST's the pre-existing EMSA5-FS processor, which is a 32-bit processor IP featuring fault tolerance based on the same open standard RISC-V. The new version of the functional safety embedded RISC-V processor, EMSA5-FS, is built for machine learning and artificial intelligence applications on standalone devices and microcontrollers used at the edge. The need for such processor cores is to meet the ever-growing market for Edge AI implementation in various IoT domains.

Initially, the EMSA5-FS processor IP came with a single-issue, in-order, 5-stage execution pipeline supporting 32-bit base embedded instructions set with a few extensions added as per the demand. With Fraunhofer coming into the light, the company realized the necessity of minor upgrades for some Edge AI projects by supporting embedded machine learning through TinyML. Following are more upgrades to the microarchitecture of the processor to offer several features suited for Edge AI workloads. 

What’s new with CAST’s EMSA5-FS Processor? 

When a new product comes to market it is important to highlight and compare the key enhancements to its predecessor. The following are some of the distinguishable features:

  1. The porting of Tensor Flow Lite, which is an open-source set of tools enabling embedded machine learning that can be seen in the Edge AI microcontrollers, smartphones, and many of the IoT implementations. This support from Fraunhofer has brought the enhanced capabilities of the processor IP to follow the thriving market for Edge AI products. Maintaining the balance between power efficiency and high performance has always been the central motive behind the latest processor design. With this significant transformation, developers can utilize this feature to run AI models, addressing latency, privacy, size, and power consumption issues.

  2. The second major upgrade comes from the addition of Zve Extensions to RISC-V which provides vector math processing for microcontrollers and embedded devices. The need for the extension on the pre-existing processor core lies with the enhanced capabilities enabling the fast execution of demanding functions like artificial intelligence and machine learning in small, low-powered, edge devices. 

[Image Credit: CAST]

“These additions to the EMSA5-FS Processor core now enable the execution of vector instructions that allow parallel processing of datasets and can consequently improve performance as well as energy efficiency,” said Dr. Andreas Weder, Group Manager of Module Integration at Fraunhofer IPMS. “Our users can now reliably implement Edge AI applications such as gesture recognition or vibration analysis.”

Final Thoughts on the EMSA5-FS Processor

The shift from Cloud to Edge data processing has impressively brought change in the way IoT applications are deployed. Faster data processing at the edge of the sensor nodes has enabled improved efficiency in time-critical applications. Sensor data analysis, gesture control, vibration analysis in consumer and industrial implementation have demanded low latency and graded performance.

For ultra-low-power and inexpensive SoC design, EMSA5-FS processor IP is well suited with its availability starting in the first half of 2022 for the Tensor Flow Lite option while the Zve extension is to follow later that year.

Featured Companies

Fraunhofer IPMS

Maria-Reiche-Str. 2
Dresden, 01109

CAST

11 Stonewall Court
Woodcliff Lake, NJ 07677

Abhishek Jadhav is an engineering student, freelance tech writer, RISC-V Ambassador, and leader of the Open Hardware Developer Community.

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