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Articles related to eInfochips

Importance of Hierarchical DFT implementation in maximizing the SoC - throughput ? Part - I - Story

November 24, 2020

Advanced Design For Test(DFT) techniques provides efficient test solutions to deal with higher test cost, higher power consumption, test area, and pin count at lower geometries.

Analog & Power

Effect of Temperature Inversion on Lower Nodes - Story

October 28, 2020

The threshold voltage is the minimum voltage required for the flow of electrons through the channel. It is denoted by VTH of a MOSFET.


Reduce DFT Footprints in ASIC Design by Addressing Test Time - Story

October 22, 2020

An Approach Using Test Channel Reduction to save Testing Cost

Analog & Power

Setup Violation Fixing in Timing Critical Complex Designs Using Late Clocking - Story

September 22, 2020

Now a days the performance of these chips and clock frequencies are going higher and higher to meet the high-speed data traffic over the internet, or intensive CPU tasks itself.

Debug & Test

Effective Reporting of UVM Transaction - Custom Transaction Printer - Story

August 21, 2020

With the increasing area and complexity of the system-on-chip(SoC) design, there is a huge responsibility and workload on verification, making it the bottleneck of the entire SoC design flow.

AI & Machine Learning

A Step by Step Guide to Voice Enabled Device Testing - Blog

June 24, 2020

It has been said that devices cannot do everything that humans can do. However, the devices that we use in our daily lives have been evolving over the last couple of decades.


High Speed PCB Design Precautions to Reduce EMI - Story

June 10, 2020

This document is written based on the practical observation of electromagnetic interference from high-speed signals and power switchers, which can cause failure in the certification process.