Rambus Advances AI/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem

By Tiera Oliver

Associate Editor

Embedded Computing Design

August 16, 2021

News

Rambus Advances AI/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem

Rambus Inc. announced the Rambus HBM3-ready memory interface subsystem consisting of a fully-integrated PHY (1) and digital controller (2). Supporting data rates of up to 8.4 Gbps, the solution is designed to deliver over a terabyte per second of bandwidth, more than double that of high-end HBM2E memory subsystems.

With a market position in HBM2/2E memory interface deployments, Rambus is ideally suited to enable customers’ implementations of accelerators using next-generation HBM3 memory.

Per the company, Rambus achieves HBM3 operation of up to 8.4 Gbps leveraging over 30 years of high-speed signaling expertise, and a strong history of 2.5D memory system architecture design and enablement. In addition to the fully-integrated HBM3-ready memory subsystem, Rambus provides its customers with interposer and package reference designs to speed their products to market.

Benefits of the Rambus HBM3-ready Memory Interface Subsystem:

  • Supports up to 8.4 Gbps data rate delivering bandwidth of 1.075 Terabytes per second (TB/s)
  • Reduces ASIC design complexity and speeds time to market with fully-integrated PHY and digital controller
  • Delivers full bandwidth performance across all data traffic scenarios
  • Supports HBM3 RAS features
  • Includes built-in hardware-level performance activity monitor
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
  • Includes 2.5D package and interposer reference design as part of IP license
  • Features LabStation development environment that enables quick system bring-up, characterization and debug
  • Enables high performance in applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems

1. https://www.rambus.com/interface-ip/ddrn-phys/hbm3/

2. https://www.rambus.com/interface-ip/controllers/memory-controllers/hbm3/

For more information, visit rambus.com/interface-ip.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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