How to Remotely Reset Your Serial SPI Memory Device, and Why
May 08, 2019
The SPI is widely used to connect microcontrollers to peripherals and memory devices in embedded systems. In particular, it is frequently used for serial NOR flash that stores executable code.
Design stability is crucially important in embedded design, the use of reset is a powerful tool for recovering from runtime errors. However, the reset pin is under pressure as memory manufacturers develop smaller packages unable to support a dedicated hardware reset pin. Thankfully, this is now less of a problem for serial Flash devices that support the new JEDEC JESD252 standard, which defines a reset mechanism that doesn’t require a dedicated reset pin.
There are many potential causes of transient errors in electronic systems, including signal integrity problems and background radiation that can corrupt memory, causing data and programming errors. These are the sort of failures that can lead to the common question: “have you tried turning it off and on again?” This may only be inconvenient for consumer devices, but it becomes a major problem for embedded systems and IoT nodes.
These systems need to run continuously with minimal down-time. Often, they are inaccessible and so they need to be able recover from failures without human intervention. Such systems will typically already use self-test mechanisms such as watchdog timers in order to detect failures and take corrective action, but this isn’t always sufficient.
Design engineers will ensure that all devices are set to a known state at power up. However, a soft reset can also be part of an error recovery strategy, so it’s important that the system as a whole is able to reset components and subsystems.
Resetting Serial Flash Memory
The Serial Peripheral Interface (SPI) is widely used to connect microcontrollers to peripherals and memory devices in embedded systems. In particular, it is frequently used for serial NOR flash that stores executable code.
The original SPI specification only had a single data wire in each direction. This was too slow to support high performance code execution directly from the serial memory. This meant that code had to be copied to SRAM before it could be run, increasing startup time and adding to system cost.
To improve the bandwidth from the original SPI specification, four or eight data signals can be used, allowing more data bits to be transferred on each clock cycle. These expanded SPI (xSPI) interfaces are defined by JEDEC in JESD251.
Modern Octal xSPI memories, such as the Adesto EcoXiP range, provide the performance required to execute code directly from the serial memory, a technique known as execute in place (XiP). This provides high performance and supports instant-on, while keeping power consumption to a minimum. It also reduces the amount of SRAM required and hence reduces system cost.
In the case of a system failure, the serial memory may need to be reset as part of the recovery process. However, pressure on manufacturers to produce smaller, lower-cost packages with a reduced pin count means that many serial memories do not have a reset pin or, if they do, it may be multiplexed with another function making it hard to use. The new JEDEC serial flash reset protocol, defined in the standard JESD252, enables control of the reset function without needing a dedicated reset pin.
Instead of a reset pin, JESD252 uses the SPI signals (clock, chip select, and serial data) to transmit a sequence that forces the target device to reset itself. During a reset sequence the clock signal is held low to distinguish the reset transaction from a normal SPI command and prevent any SPI commands being sent, using the chip select signal as a clock for the target device. A specified sequence of transitions is transferred on the data pin to prevent erroneous resets caused by noise.
Adesto shipped the first serial NOR flash memories to support JESD252 and it’s also available in its EcoXiP, which features an Octal SPI interface to provide higher performance than Quad interfaces. Execution performance is further optimized by performing sequential instruction fetches without needing to send an address for every read. EcoXiP also has features to reduce power consumption and provide greater security.
Building Better Designs
Using XiP, you will be able to provide the performance you need at lower power and cost. While XiP requires a compatible memory interface on the microcontroller, a growing number of manufacturers are adding support for this. By specifying serial flash memory devices that support the JESD252 serial reset protocol, you will be able to develop more reliable and stable products, resulting in greater customer satisfaction.