MIPI D-PHY v3.0 Doubles Data Rate of Physical Layer Interface and Extends Power Efficiency

By Tiera Oliver

Associate Editor

Embedded Computing Design

September 03, 2021

News

MIPI D-PHY v3.0 Doubles Data Rate of Physical Layer Interface and Extends Power Efficiency

The MIPI Alliance announced an update to its MIPI D-PHY specification for connecting megapixel cameras and high-resolution displays to application processors.

According to the company, Version 3.0 doubles the data rate of D-PHY’s standard channel to 9 Gigabits per second (Gbps), while extending the power efficiency of the specification for smartphone, Internet of Things (IoT), and automotive camera and display applications.

MIPI D-PHY has been implemented as the physical-layer interface for cameras and displays in smartphones because of its cost-effective flexibility, high speed and low power. Due to these attributes, the specification has also been applied to an array of other use cases such as drones, very large tablets, surveillance cameras, and industrial robots, as well as automotive applications, including camera sensing systems, collision avoidance radars, in-car infotainment and dashboard displays, with the support of proprietary bridging solutions.

D-PHY v3.0 doubles the specification’s speed to 9 Gbps for the standard channel (and 11 Gbps for its short channel), enabling support for the latest ultra-high-definition displays and beyond. In tandem with the boost in data rate, D-PHY v3.0 introduces a Continuous-Time Linear Equalizer (CTLE) on the receiver side of a connection to maintain the interface’s superior power efficiency. D-PHY v3.0 is fully compatible with previous versions of the MIPI specification.

In conjunction with the release of D-PHY v3.0, MIPI Alliance also announces version 2.1 of MIPI C-PHY, which provides high throughput and suitable power efficiency to connect displays and cameras to application processors. The specification supports symbol rates up to 6 Gigasymbols per second (Gsps), equivalent to 13.7 Gbps, over the standard channel and up to 8 Gsps over the short channel. A new 64-bit PHY Protocol Interface (PPI) in v2.1 provides a wider bus between C-PHY and a chip’s core logic for better support of higher-performance applications. The new version of the interface is fully compatible with previous versions of C-PHY.

In addition to the added features, the new version of the C-PHY specification replaces objectionable terms with ones that more accurately reflect the functions of technical devices. 

MIPI's upcoming developers conference (MIPI DevCon), on 28-29 September 2021, will feature a variety of technical sessions and member demonstrations on MIPI specifications in application spaces such as mobile, the IoT, automotive, and 5G. Visit https://www.mipi.org/devcon/2021/register for complimentary registration.

For more information, please visit www.mipi.org.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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