Why UCIe Is an Integral Interconnect for Multi-Die Systems
November 08, 2022
Blog
As multi-die systems grow more prevalent in the semiconductor space, the Universal Chiplet Interconnect Express (UCIe) specification is taking center stage.
Thanks to its support for high bandwidth and high performance, along with its flexibility, UCIe is poised to become a gold standard leading a new wave of innovation.
Traditional monolithic SoCs are reaching power, performance, and area (PPA) limitations for data-intensive applications like artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) for hyperscale data centers. Answering the call are multi-die systems, consisting of individual dies, or chiplets, that enable scaling of performance by supporting discrete functions or multiplying the capabilities of individual dies. They’re integrated together in a standard or an advanced package.
While monolithic chips are approaching the reticle ceiling for manufacturing, multi-die systems can deliver more system functionality, enhanced PPA, better yield, as well as lower cost to support advanced designs. UCIe brings to the table support for customizable, standards-based, package-level integration of chiplets. An open specification, it defines the interconnect between chiplets within a package. Its characteristics are well suited for the requirements of multi-die systems.
Supporting Today’s and Tomorrow’s Bandwidth Demands
While several different standards have emerged to address the challenges of multi-die system, UCIe is the only standard with a complete stack for the die-to-die interface. The specification supports 2D and 2.5D packages, with 3D packages expected in the future. Other standards focus only on specific layers of the protocol stack and lack a comprehensive specification for the complete die-to-die interface that ensures interoperability between implementations.
UCIe accommodates the bulk of designs today from 8 Gbps to 16 Gbps per pin; it also accommodates designs at 32 Gbps per pin for future high-bandwidth applications, like networking and hyperscale data centers. There are two package variants to choose from. UCIe for advanced packages supports silicon interposer, silicon bridge, and redistribution layer (RDL) fanout, while UCIe for standard packages supports organic substrate and laminate.
The UCIe stack itself consists of three layers. At the top is the Protocol Layer, which ensures maximum efficiency and reduced latency through flow control unit-based (FLIT-based) protocol implementation. The Protocol Layer supports popular specifications including PCI Express® (PCIe®), Compute Express Link (CXL), and/or user-defined streaming protocols. At the second layer, the protocols are arbitrated and negotiated, and link management occurs through a die-to-die adapter. This layer implements error detection and correction functionality based on cyclic redundancy check (CRC) and a retry mechanism. The PHY marks the third layer, specifying the electrical interface with the package media. In the PHY layer, the electrical analog front end (AFE), transmitter and receiver, and sideband channel allow parameter exchange and negotiation between two dies. Logic PHY implements the link initialization, training and calibration algorithms, and test-and-repair functionality.
How Proven IP Enables Robust Die-to-Die Links
To ease the adoption of UCIe for multi-die system designs, designers can turn to PHY, controller, and verification IP. PHY IP that supports both standard and advanced packaging options offers flexibility, while in advanced FinFET processes can support high-bandwidth, low-power, and low-latency die-to-die connectivity. Controller IP enables solutions aligned to commonly used protocols like PCIe and CXL and can enable latency-optimized network-on-chip (NoC)-to-NoC links with streaming protocols; for example, bridging to CXS interfaces and to AXI interfaces. Finally, verification IP that supports various designs under test (DUT) at each layer of the full stack can help accelerate runtime, as well as debug and coverage closure for the designs.
The right set of PHY, controller, and verification IP can lead to reliable, robust die-to-die links with low latency and high energy efficiency. Built-in testability features for known good dies and CRC or parity checks for error correction support chip yield and quality targets.
Several industry leaders, including Synopsys, are contributing to the evolution of the UCIe specification. With the deep experience and dedicated efforts of the contributor members, UCIe is poised to be a key enabler fostering the continued growth of multi-die system designs.
Manuel Mota is a senior staff product marketing manager in the Synopsys Solutions Group. He has extensive experience in the semiconductor industry, with expertise in high-speed IO protocols, analog and mixed-signal designs, and wireless IP. Manuel has a Ph.D. in electronics from Instituto Superior Tecnico.
Manuel Mota is a senior staff product marketing manager in the Synopsys Solutions Group. He has extensive experience in the semiconductor industry, with expertise in high-speed IO protocols, analog and mixed-signal designs, and wireless IP. Manuel has a Ph.D. in electronics from Instituto Superior Tecnico.
