SmartDV Announces New Line of Design IP Controllers for High-Speed Communications

December 14, 2020

Press Release

SmartDV Announces New Line of Design IP Controllers for High-Speed Communications

SmartDV now offers a portfolio of silicon-realized, minimal area controller Design IP for Mobile and Mobile-Influenced (MIPI) and Universal Serial Bus (USB) interfaces.

SmartDV Technologies acquired the Design IP business and products from an engineering services company, for an undisclosed amount.

Under terms of the acquisition agreement, SmartDV now offers a portfolio of silicon-realized, minimal area controller Design IP for Mobile and Mobile-Influenced (MIPI) and Universal Serial Bus (USB) interfaces. All are implemented in numerous chip design projects and a variety of consumer electronics devices. They include:

MIPI

• MIPI Camera Serial Interface (CSI-2) transmitter and receiver Controller Design IP for C-PHY and D-PHY
• MIPI Display Serial Interface (DSI) and DSI-2 transmitter and receiver Design IP for C-PHY and D-PHY
• MIPI CSI-3 Host and Device Design IP
• Universal Flash Storage (UFS) interface 2.1 and 3.0 Host and Device Design IP
• MIPI Unified Protocol (UNIPRO) Controller 1.6 and 1.8 Design IP
• I3C interface Master and Slave Controller Design IP

USB
• Silicon-proven and USB-Implementers Forum (USB-IF) certified
-- USB 1.1/2.0 Device Controller
-- USB3.x 5G Device Controller
-- USB3.x 5G Host Controller
-- USB3.x 5G Hub Controller
-- USB3.x 5G Dual-Role Controller

• USB-IF certified
-- USB3.x 10G Device Controller

• Verified and FPGA Validated
-- USB On-the-Go (OTG)
-- USB SuperSpeed Inter-Chip (SSIC)
-- USB2.0 xHCI Host Controller

• Design Ready
-- USB4.0 Device Router

The Controller Design IP offerings are compliant with MIPI, UFS, and USB standards. Licenses include validation platforms along with firmware support to functionally validate chip design prior to tape out and mitigate risk.

All Controller Design IP is pre-verified and delivered as a comprehensive solution complete with a verification suite, clock domain crossing, synthesis, and logic equivalence checking constraints and waivers, as applicable. They are reusable at the system-on-chip (SoC) level and proven interoperable with partner PHY solutions.

The latest additions to the SmartDV Design IP portfolio are available now and backed by an experienced R&D team who work individually with each user installation.  Pricing is available upon request.

For more information, visit: www.Smart-DV.com

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