Smart DV Releases Verification IP Suite for Arm AMBA Protocol
July 10, 2020
Assertion IP and SimXL synthesizable transactors for SoC and system-level testing are also part of the release.
SmartDV Technologies has released verification IP solutions for the Arm’s AMBA CHI, CXS, and LPI bus protocols. Assertion IP and SimXL synthesizable transactors for SoC and system-level testing are also part of the release.
Configurable bus functional models (BFMs), a protocol monitor, and library of integrated protocols checks are included in with the AMBA verification IP, and support SystemC, the universal verification methodology (UVM), and the open verification methodology (OVM)
SmartDV automated compiler-based technology provide quick compliance with standard protocol specifications, and can be used in coverage-driven chip design verification flows via simulation, emulation, FPGA prototyping, or formal verification.
“Verification engineers require high-quality Verification IP solutions for each of them to connect and manage a SoC's functional blocks, whether its coherent processors and high-performance interconnects, point-to-point communications or handling clock and power features,” said Deepak Kumar Tala, Managing Director of SmartDV. “SmartDV meets this need so verification engineers can verify and debug their designs quickly, easily and more effectively."
These additions to the company’s Arm AMBA protocol verification IP suite are available now. For more information, visit Smart-DV.com.