OpenHW Ecosystem Implements Imperas RISC-V Reference Models
July 21, 2020
Imperas announced the OpenHW Group established the CORE-V processor verification test bench, using Imperas' RISC-V reference model.
Imperas Software announced the OpenHW Group, a not-for-profit that facilitates collaborations between hardware and software designers in open source IP development, established the CORE-V processor verification test bench, using Imperas’ RISC-V reference model. The partnership formed to deliver higher quality IP cores to the OpenHW Group ecosystem and open source hardware community.
“The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption,” said founder and CEO at OpenHW Group Rick O’Connor, in a press release. “Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.”
There are four key elements to processor verification: a DV plan, tests to run, device-under-test (DUT) to test, and a reference model for comparison with discrepancy debug and resolution. A DV team can only collaborate and complete tasks if all of these steps are completed and accounted for.
Often, random instruction steam generators are employed, like Google open source project, as a DV technique to test complex states and corner cases. Per the release, RISCV-DV ISG as a test source and can be found on GitHub at https://github.com/google/riscv-dv. By setting up the SystemVerilog test environment to run the tests in a side-by-side configuration, with the DUT and reference model, a step-and-compare methodology can be enabled. By doing so, developers can avoid inefficiencies of logfile based methods and supports direct analysis of problems that arise.