Lattice CrossLink-NX FPGA Integrates Mixel MIPI D-PHY IP

May 19, 2020

Press Release

Lattice CrossLink-NX FPGA Integrates Mixel MIPI D-PHY IP

Low-power Lattice FPGA to support D-PHY v1.2 with 2.5 Gbps per lane.

Mixel's MIPI D-PHY IP solution has been integrated with Lattice Semiconductor's 28 nm Crosslink-NXTM FPGAs. The D-PHY v1.2 link supports between one and four lanes at 2.5 Gbps per lane for  a maximum aggregate data rate of 10 Gbps per instance.
The Mixel MIPI D-PHY Universal IP provides transmit and receive functionality for MIPI CSI-2 and MIPI DSI applications. Proprietary features allow the solution to reduce standby current and wake-up time.
Lattice was able to achieve first-time silicon success when incorporating the IP into their latest-generation devices based on the FD-SOI Lattice Nexus FPGA platform. An earlier generation of Mixel D-PHY Universal IP was integrated into the CrossLink Programmable ASSP.
To  date,  Mixel MIPI IP has  been silicon proven in nine  nodes from eight foundries.
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