Codasip Releases the First Linux-capable RISC-V Core Bk7 Optimized for Domain-Specific Applications

July 21, 2020

Press Release

Codasip Releases the First Linux-capable RISC-V Core Bk7 Optimized for Domain-Specific Applications

New Codasip Bk7 64-bit core with 7-stage pipeline and able to support Linux.

Codasip announced the official release of Bk7. According to the company, the Bk7 is the most advanced core in the Codasip family of RISC-V processor IP to date, built with customization and domain-specific optimization in mind.

The Bk7 is ideally suited for most modern applications, from security to real-time AI processing, especially where embedded Linux is required.

The Codasip Bk7 is a 64-bit processor core with a single in-order 7-stage pipeline, fully compliant with the RV64IMAFDC instruction set architecture (ISA). As with all Codasip Bk cores, the open RISC-V standard makes it possible to configure and extend the core to fit the customer's domain-specific needs.

RISC-V-based processors are customizable by design, but the customizability presents a challenge for chip manufacturers in terms of time-to-market. The Codasip Studio toolset, used to design the Bk7, aids in this process by automatizing all the mentioned tasks. Studio uses a single high-level description of a core written in CodAL, a C-like language. Once this description is updated with any required custom changes, Studio will use it to generate a complete customized HDK and SDK, including a full UVM verification environment-everything needed to deploy the core. With Bk7, Codasip has taken this approach a step further by developing a new, module-based architecture for CodAL editing.

The off-the-shelf configuration of Bk7 includes support for the RISC-V atomic and floating-point extensions (both single and double precision), a memory management unit (MMU), and support for privilege modes needed for richer operating systems including Linux.

Bk7 also features an internal interrupt controller, dynamic branch prediction (BHT, BTB, RAS), JTAG and RISC-V debug, and standard bus interfaces (AMBA). In-built customizable options include the branch predictor, instruction and data caches, store buffer, and others. According to the company, future releases of Bk7 will include tightly coupled memories, dual issue microarchitecture, and multicore support.

The Bk7 comes in a package that contains all supporting tools to deploy the core: the CodAL description (fully editable in Codasip Studio), RTL code of the default configuration, the CodeSpace IDE to write software for the core, C compiler (LLVM and GCC), source files and compilation guide for Linux, and Linux boot demo SoC.

Bk7 is available for licensing now through the Codasip sales teams worldwide.

For more information, visit: www.codasip.com or www.riscv.org

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