For the Professional Maker: Explore RISC-V with the VEGAboard
February 19, 2019
RISC-V is an open instruction set computing architecture. It has its roots in academia, and is based on the RISC, or Reduced Instruction Set Computer paradigm.
If you’ve been paying attention to the hardware scene recently, you’ve likely heard discussion of RISC-V, but it’s less likely that you understand what it means, and even less so that you’ve actually worked with it. To get the basics out the way, RISC-V is pronounced “risk-five,” and is an open instruction set computing architecture. It has its roots in academia, and is based on the RISC, or Reduced Instruction Set Computer paradigm. According to the RISC-V foundation, this architecture is meant to “[Enable] a new era of processor innovation through open standard collaboration.”
While this definition sounds excellent, it still leaves a few practical questions. How do you start working with it? Where’s the ecosystem? How does it compare to other architectures? As far as ecosystem, it is still in its infancy, however, the foundation supporting RISC-V consists of over 100-member organizations, including such names as NXP, MicroChip, Google, and NVIDIA. With such heavy-hitters onboard, and a long-range goal of innovating for the next 50 years, it would seem that things here will improve in the future.
One way you can experiment with this architecture right now—or hopefully soon as they are currently out of stock after giving away 1,500 of their development boards for free—is via the Open-ISA VEGAboard. At the heart of this device is a WiSoC containing four processing cores. What’s unusual about this configuration is each core is different, consisting of an ARM Cortex M4, ARM Cortex-M0+, RISC-V RI5CY, and RISC-V ZERO_RISCY CPU. This allows users to configure these cores to run in different combinations in order to experiment and compare the use of ARM and RISC-V processors. Notably, so as to simplify the design, the M4 and RISCY cores share the same memory bus with no arbitration. While both can be enabled at the same time, memory bandwidth drops in half, so generally this WiSoC will be used 2 cores at a time.
Supporting this module is the VEGAboard itself, which features female headers for Arduino Uno-style expansion shields and other peripherals, an onboard I2C accelerometer/magnetometer, and a light sensor. It also has several ways to power it, multiple LEDs, user buttons, and wireless communication is available in the form of BLE and IEEE 802.15.4. These onboard accessories mean that a wide variety of experiments can be performed with no external hardware added, though expansion is widely available when needed.
The necessary software to program the device under Linux, Max, and Windows is available on the Open-ISA startup page, which outlines five steps to get started, and even provides video tutorials. Board documentation is available on GitHub, and there is a community forum setup to answer your queries. When you’re ready to take the leap and start experimenting with RISC-V and perhaps compare performance to ARM-based chips, the VEGAboard looks like a great way to get started. It will be interesting to see how this device is used, and how the RISC-V ecosystem itself continues to develop around this and other innovative systems into the future.
Jeremy S. Cook is a freelance tech journalist and engineering consultant with over 10 years of factory automation experience. An avid maker and experimenter, you can follow him on Twitter or see his electromechanical exploits on the Jeremy S. Cook YouTube Channel!