Product of the Week: Cadence Spectre FX FastSPICE Simulator

June 22, 2021


Product of the Week: Cadence Spectre FX FastSPICE Simulator

As SoCs and memory provide more capabilities, they also become more complex. And the more complex they become, the more difficult the verification process is for chip designers. They need increasingly advanced simulation technology that ensures each circuit meets the chip’s specifications and requirements.

Cadence’s Spectre FX FastSPICE circuit simulator is designed for pre- and post-layout verification of advanced-node memory and large-scale SoC designs. Integrating a FastSPICE engine that is built from the ground up for full chip and subsystem-level design verification, the new tool leverages static and dynamic circuit checking; Monte Carlo, transient, ALTER, and DC and OP analyses; checkers; and sweeps to simulate the functionality, timing, and power of analog, RF, and mixed-signal circuits.

According to the company, Spectre FX FastSPICE provides a 3X performance improvement over other modern FastSPICE simulators at the same or better accuracy. This is aided by an RC matrix solver and reduction algorithms, advanced partitioning, and support for up to 32-core multicore processor with multi-threading capabilities, which allows simulations to be parallellized for improved simulation efficiency and productivity. It also integrates Tcl interactive runtime debugging and Save-Restore features that further minimize computation time.

The simulator offers common language support, common models, and also integrates with other Cadence tools. Built on the same technology infrastructure as the rest of the Spectre Simulation Platform, which includes Spectre X, Spectre AMS Designer, Virtuoso ADE Integration, and other tools, Spectre FX completes the Cadence verification chain, from cell-level to chip-level verification.

Cadence Spectre FX FastSPICE Circuit Simulator in Action

Spectre FX FastSPICE accepts input formats that include Spectre and SPICE netlists, Verilog-A 2.0, DSPF/SPF/DPF parasitics, Tcl scripts, and VCD or digital vector files. It can ouput into PSF and FSDB waveforms.

Out of the box, minimal platform tuning is required for FastSPICE verification of any given application. This is thanks in part to a suite of presets that allow designer to predictably control tradeoffs between simulation accuracy and performance. These presets are tailored to differentt verification tasks like timing checks or leakage current measurement, either at the block level for fine-grained control.

During large post-layout simulations, the FX circuit simulator uses the aforementioned advanced RC reduction to handle tens of millions of RC parasitics, providing either direct inclusion or parasitic back annotation in extracted SPICE, DSPF, or SPEF formats. As stated, transistor-level static annd dynamic circuit checking commands enable designers to detect conditions such as high impedance nodes, leakage paths between power supplies, and device-level timing errors. These circuit checks can be applied to the entire design or specific blocks.

Output formats include PSF and waveform formats, while output parasitic files can be a flat or hierarchical netlist included in the main netlist, or can be back-annotated into a pre-layout netlist for further debugging capabilities via SPICE and FastSPICE modes. These modes also allow users to establish a golden reference during the verification processs.

As mentioned, the Tcl interactive mode proviides advanced debugging features for chip and memory designers. This includes the ability to add new probes, start and stop simulations, and add new design elements like voltage sources. Integration with the Virtuoso ADE Product Suite enables Spectre FX users to easily adopt existing Spectre and SPICE flows, common-use models, and waveform analysis, cross-probing, and so on. Meanwhile, compatibility with the Cadence Virtuoso Custom IC design platform accepts data from the simulation environment for transistor-level analysis.

Getting Started with the Cadence Spectre FX FastSPICE Circuit Simulator

The Cadence Spectre FX FastSPICE Circuit Simulator uses RHEL 7.4 as its build OS, but supportts RHEL 7.4 or greater, RHEL 8, or SLES 12.

Cadence engineers are available to address technical questions or provide custom training, which is also available via more than 30 Internet Learning Series (iLS) online courses, rapid adoption kits, software downloads, and more. 

For more information about Cadence Spectre FX FastSPICE Simulator, visit or, check out the introduction to the tool by Cadence's Senior Vice President of Custom Products Tom Beckly, or navigate to any of the resources below.


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