Product of the Week: Texas Instruments' Sitara AM6442 Real-Time Networked Processor

May 04, 2021


Product of the Week: Texas Instruments' Sitara AM6442 Real-Time Networked Processor

Increased demand for functionality in Industry 4.0 and 5.0 environments means that embedded systems are becoming more complex. And as system capabilities grow, a single processor often won’t cut it. So Texas Instruments keeps adding others.

The T.I. Sitara AM6442 is a part of the AM64x family of dual-core 1 GHz Arm Cortex-A53-based real-time networked processors that also integrate two dual-core 800 MHz Arm Cortex-R5F CPUs, a 400 MHz Arm Cortex-M4F MCU for implementing functional safety features, and two programmable real-time units (PRUs) for managing the device’s Ethernet time-sensitive networking-enabled (Ethernet TSN-enabled) industrial communications subsystems. As a result of this compute fusion, systems based on the AM6422 are able to balance application processing, real-time control, and communications tasks of platforms like PLCs, motor drives, and industrial robots.

To support all of that processing, the AM6442 Sitara processor features tightly-coupled memory (TCM) cache memory banks and SRAM partitioning of the up to 2 MB of on-chip ECC RAM. This RAM can be divided into eight banks of 256 KB, each of which can be allocated to a single core to help isolate software tasks. The SoCs also include a general-purpose memory controller (GPMC) that supports 1600 MTps LPDDR4 and DDR4 memories over a 16-bit data bus.

These and other characteristics of the AM6442 processors, such as the data movement subsystem service (DMSS), establish low-latency data paths between external peripherals that require tight control loops and the resources they need on the SoC. Some of the internal peripherals included on the chip that also contribute to this determinism are two 64-bit industrial Ethernet peripherals (IEPs) for time stamping and synchronization; 18 sigma-delta filters; 6x multi-protocol position encoder interfaces; and enhanced PWMs.

This and more in a 16 nm process that consumes less than 2 W.

The Texas Instruments Sitara AM6442 Real-Time Networked Processor in Action

Of course, this functionality means little if the systems housing the T.I. AM6442 SoC can’t communicate efficiently with the outside world. Here, the device supports a range of industrial connectivity options, beginning with a switch that supports IEEE 1588 precision time protocol (PTP) for up to 1 GbE TSN. This is managed by the aforementioned PRU-ICSSG, which also provides the ability to run EtherCAT, PROFINET, EtherNet/IP, and other protocols.

Other high-speed interfaces offered by the Sitara include PCIe Gen2 annd USB 3.1-Gen1, while general connectivity and control interfaces include:

  • 9x configurable UARTs including one 16550-compatible UART that supports 12 Mbps PROFIBUS
  • 7x multi-channel SPIs
  • 8x Fast SPI cores (6 Rx, 2 Tx)
  • 3x GPIOs
  • 3x Enhanced Capture (ECAP) modules
  • 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x CAN modules with CAN-FD support

All of this networking support is backed by a comprehensive security suite, which starts with a Hardware-enforced (Root-of-Trust) that provides the foundation for a secure boot process. The AM6442 SoCs also support Arm TrustZone-based Trusted Execution Environments (TEEs).

A session-aware cryptographic engine is compatible with all standard encryption schemes and key lengths, while a security co-processor provides key and interconnect security on the device.

Getting Started with the Texas Instruments Sitara AM6442 Real-Time Networked Processor

The AM6442’s integrated Cortex-A53 cores offer ideal computing properties for Linux applications, and a Linux image can be booted from DDR. Linux and real-time Linux development environments and tools for working with the AM6442 can be found in the T.I. Processor SDK, which is updated annually with the latest Long-Term Support (LTS) Linux kernel, bootloader, and Yocto file system.

Using the SDK, developers can get complex systems on-line quickly by isolating Linux applications from real-time streams via the configurable memory partitioning mentioned previously. This goes so far as to allowing the A53 cores to be deployed jointly or independently based on the configuration of internal SRAM blocks.

Information on terminal configuration and functions, pin diagrams, and more engineering resources are available on the T.I. website, where you can also find mechanical, packaging, and ordering information. Design tips are also available on TI E2E support forums, in the AM64x GP EVM User's Guide or in the resources below.




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