Microchip Releases Libero SoC Design Suite for Latest FPGA Families
January 29, 2019
Microchip Technology Inc. released its Libero SoC version 12.0, providing one unified design suite for the most updated FPGA families, including the new PolarFire FPGAs.
CHANDLER, AZ. Microchip Technology Inc. released its Libero SoC version 12.0, providing one unified design suite for the most updated FPGA families, including the new PolarFire FPGAs.
Libero SoC v12.0 supports FPGA Hardware Breakpoint (FHB) for RTG4 and PolarFire devices, PCIe debug support for PolarFire and constant transceiver eye monitoring with SmartDebug. It enhances DDR memory performance by an average of 29 percent in high-effort mode and 39 percent in regular-effort mode.
Libero SoC v12.0 also decreases design flow runtimes by 60 percent for timing, 25 percent for place and route and 18 percent for power results and provides results in fewer design iterations while improving productivity. It also garners an average increase of four percent in quality of results for larger designs and a 10 percent improvement for the PolarFire MPF300/TS-1 device.
“Libero SoC v12.0 is the result of our determination to offer a comprehensive, easy-to-adopt, easy-to-learn FPGA design suite,” said Rajeev Jayaraman, Microchip’s Microsemi subsidiary’s vice president of software for the FPGA business unit. “This latest release is focused on delivering the many essential elements needed for efficient design implementation, while further enabling the growing adoption of the low-power PolarFire family across each of our key market segments.”
For more information, please visit www.microchip.com.