Imperas to Demonstrate Solutions for RISC-V Processor Verification and Extensions at Embedded World, Nuremberg 2020
February 24, 2020
We will be co-sponsoring the RISC-V Foundation stand at the Embedded World Exhibition and Conference in Nuremberg, 25-27 February 2020. Hall 3A, stand 536.
We'll be discussing all the latest demonstrations and virtual platform technology for RISC-V based designs, including verification and custom instruction as well as support for the latest RISC-V specifications for Vectors and Bit Manipulation.
In addition to exhibiting on the booth, we will also present two technical papers:
- Impact of RISC-V adaptability on SoC verification methods – by Lee Moore, Lead Engineer at Imperas
Tuesday 25 February, track session #10.3 @15:00
The verification challenges for RISC-V processors and SoCs will be presented.
Specific verification flows including new test and instruction stream generators, reference models and metrics will be presented in detail, including the results of using these flows on real processor IP and SoCs.
- Virtual platform-based development environments for low power, mixed level safety-critical systems – by Larry Lapide, VP Sales at Imperas
?Wednesday 26 February, track session #4.3.1 @15:00
Discussing the virtual platform methodology employed by SAFEPOWER. Unique tools developed to provide observability into the hypervisor-based system are described, as well as the methods for providing timing and power estimation with sufficient accuracy.
For more information or to meet with us to discuss how to verify the RISC-V cores in your next design at Embedded World please get in touch here.