Achronix Speedster7t FPGAs Suit AI/ML Apps
May 21, 2019
Achronix has now developed a new FPGA family that claims to meet the demands of artificial intelligence/machine learning (AI/ML) and high-bandwidth data acceleration applications.
The spotlight on FPGAs seems to come and go. Xilinx made quite a splash a few years ago with its ARM-based Zynq launch and frankly, has remained in that spotlight. Quicklogic recently made an announcement with SiFIve regarding FPGA templates using RISC-V. Now the attention has turned to Achronix Semiconductor, a provider of FPGA-based hardware accelerators and high-performance FPGA IP, aka eFPGA.
Achronix has now developed a new FPGA family that claims to meet the demands of artificial intelligence/machine learning (AI/ML) and high-bandwidth data acceleration applications. Called the Speedster7t family, the devices are based on an optimized architecture that offers ASIC-like performance, but with the flexibility of an FPGA.
Manufactured on TSMC’s 7nm FinFET process, the Speedster7t FPGA family features a 2D network-on-chip (NoC), machine learning processors (MLPs), and an array of compute-engine blocks. The devices are designed to accept massive amounts of data from multiple high-speed sources, distribute that data to programmable on-chip algorithmic and processing units, and then retrieve those results with the lowest possible latency. The various interfaces, including GDDR6, 400G Ethernet, and PCI Express Gen5 are all interconnected to deliver that ASIC-level bandwidth.
At the heart of Speedster7t FPGAs are a massively parallel array of programmable compute elements within the new machine learning processors (MLPs). The MLPs are highly configurable, compute-intensive blocks that support integer formats from 4 to 24 bits and various floating-point modes including direct support for TensorFlow’s 16-bit format as well as the supercharged block floating-point format that doubles the compute engines per MLP. The MLPs are tightly coupled with embedded memory blocks, eliminating the traditional delays associated with FPGA routing to ensure that data are delivered to the MLPs at the maximum performance of 750 MHz.
The Speedster7t FPGA devices range from 363K to 2.6M equivalent 6-input LUTs. The first devices and development boards for evaluation will be available in Q4 2019. The ACE design tools that support all of Achronix’s products are available today.