RISC-V Summit 2023: Embedded Editor Report, Day 2

November 09, 2023

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Everyone is buzzing about the amazing excitement and good vibes of this year’s RISC-V Summit, hosted by RISC-V International. The talk around the coffee bar is all about growth, opportunity, and possibility.

In a release, Calista Redmond, CEO of RISC-V International, said, “The biggest takeaway for the RISC-V community this year is that we’re going to see RISC-V everywhere. More and more industries and companies are turning to RISC-V to innovate faster and take advantage of the vibrant culture of collaboration.”

And in every meeting I had here in Santa Clara, that was the message: Look out world, RISC-V is coming.

You can see the momentum in the sheer volume of announcements coming out of the show:

• Andes and Vector collaborated to propel RISC-V AUTOSAR software for automotive.
• Ashling announced RiscFree C/C++ SDK support for the newly launched Synopsys ARC-V RISC-V ISA based processors.
• BeagleBoard.org launched the new BeagleV-Fire single board computer.
• Codasip unveiled its 700 family of RISC-V cores and introduced a commercial implementation of the advanced security mechanism CHERI.
• Microchip recently highlighted its expanded portfolio of RISC-V solutions. 
• OpenHW Group announced the CORE-V CVA6 Platform project for RISC-V development and testing.
• Qualcomm is collaborating with Google to bring a RISC-V based wearables solution for use with Wear OS by Google.
• SiFive debuted its Performance P870 and Intelligence X390 RISC-V products for generative AI and ML applications.
• Synopsys unveiled its new RISC-V ISA-based ARC-V Processor IP.
• Ventana introduced Veyron V2, a data center-class RISC-V processor and platform, and partnered with Imagination Technologies on RISC-V CPU and GPU solutions.

And that’s not even all of them.

In his opening keynote this morning, Mark Himelstein, CTO of RISC-V International, drilled down through several aspects of the fast-growing RISC-V ecosystem. Very interesting to the crowd were the Android and Linux builds that are happening, thanks to Google and Red Hat getting involved. He also called out RTOS integrations that are driving innovation and said that RICV-V Platforms will be the highest priority for development in 2024.

Simon Davidmann, CEO, Imperas, spoke about the importance and competitive advantage that is to be found in custom instruction sets available by using RISC-V, but he cautioned that the freedom to innovate also comes with the responsibility and necessity of additional verification.

Stephen Watt, distinguished engineer and VP, Office of the CTO at Red Hat, next took the stage and outlined his vision for the future of RISC-V in AI, Edge, and Next-gen infrastructure. Oh, and Red Hat Linux. He drilled down into Fedora, the Linux model for RISC-V that he said will allow for platform development. What’s more Red Hat has joined OpenHW and the RISE Project to contribute to those open source collaboration projects, in addition to RISC-V International.

There were further keynotes from Charlie Su, CTO and President of Andes Technology, who talked about RISC-V and AI; Ron Black, CEO of Codasip, who opened our eyes to the gigantic risks of unsecured memory (70 percent of breaches are memory related, he said!), and how CHERI is solving that problem; and Ian Steff, CEO and President of mySilicon Compass, and former US Secretary of Commerce outlined the Federal CHIPS for America Act, which is ready to distribute billions of dollars to support and incentivize innovation in embedded.

“RISC-V is similar to the swap from vacuum tubes to transistors,” Steff said. And there is funding available to encourage its growth.

There’s more to come from the RISC-V Summit over the next few weeks, but keep your eyes peeled. RISC-V is only gaining ground.

Click here to ready the Day One Roundup.