Open source RISC-V architecture is changing the game for IoT processors
February 26, 2018
The power of open source, the freedom it enables, and the communities that it generates are gaining traction in the hardware world. Here is an introduction to RISC-V and the opportunities it opens.
Over the past decade, open source software has been one of the biggest catalysts in the tech world. Today, the power of open source, the freedom it enables, and the communities that it generates are gaining traction in the hardware world too. For these reasons, RISC-V is gaining huge popularity. Here is an introduction to RISC-V and the opportunities it opens.
RISC-V is an open instruction set architecture (ISA) originally developed in the Computer Science Division at the University of California, Berkeley. It, in turn, is based on the popular reduced instruction set computing (RISC) principles, just like ARM and MIPS and other common commercial processor architectures.
The project took form in 2010, but since then has grown into a massive global collaboration, spanning multiple universities and industry. Coherency is provided by the non-profit RISC-V Foundation, which both guides the underlying ISA specification and acts as the marketing engine to promote the RISC-V approach.
To be clear, the RISC-V ISA is just what it says, an architectural specification of instruction sets, i.e. not an actual processor design. From that open source ISA, numerous academic and industrial teams have created a multitude of different processor designs, all of which essentially talk the same language. A quick read of the RISC-V Foundation website illustrates the numerous processor implementations available, from full open source processor designs such as Rocket, Orca, and PULPino, and commercial processor cores from companies such as SiFive, Codasip, Andes, and Cortus.
This wide suite of modern processor implementations, scaling from simple IoT processors right up Linux-executing application processors, all based on a common ISA, reflects the key strengths of the RISC-V approach compared to a closed commercial ISA, i.e. a freedom to differentiate and a freedom to choose & change processor supplier without suffering painful product re-architecture.
It’s free so it must be RISCky, no?
At this point, it is prudent to do a reality check and look at the factors that influence processor choice in a new product design. As with most design decisions, there are numerous technical and commercial factors, some based on hard criteria, others based on more difficult to quantify aspects.
The technical criteria is self-evident: does the processor have the required horse power, is it scalable for future generations, does it match the power envelope, does it provide the required level of security, is there a good (and familiar) software development / debug environment, can we leverage our legacy code base. The commercial criteria considers costs such as die area (both gate count and memory sizes), royalties, and, of course, overall license fees. It also considers other business aspects including vendor lock-in, warranties and indemnities, commercial reporting obligations, legal rights to modify, etc.
Considering all these factors, most designers have tended to adopt a “safe” option, usually one of the proprietary commercial processors and often sticking with a family they have previously used. However, many companies, at the strategic level, are uncomfortable with the increasingly limited choice of robust commercial processor IP vendors. There is a growing desire for more commercial freedom, to break-away from closed ISA lock-in, not only in terms of license and royalty fees but also in terms of freedom to differentiate.
This desire has given wind to RISC-V’s sails. The RISC-V open source ISA offers companies a realistic option to move beyond the common commercial options without taking excessive strategic risk, the same way Linux, FreeRTOS, and many other open source RTOS are today indisputable alternatives to commercial OS. This is especially true for the smaller embedded processors, as typically employed in consumers IoT devices. A number of notable tier one companies, including Western Digital and nVidia, have already publicly declared their intent, or indeed are already in mass production, and many more companies are evaluating RISC-V, some with very advanced designs under wraps.
CEVA’s experience with RISC-V
Like these companies, CEVA has been intrigued by the potential of RISC-V, especially in regards to our RivieraWaves Wi-Fi and Bluetooth IPs (Figure 1). These communication technologies require a small processor to execute the protocol stacks and our aim was to create an integration-ready reference platform that offers our customers freedom in the choice of processor. In terms of requirements, the horse-power needs are modest, even for advanced Wi-Fi configurations, since the IPs have been architected for very low power operation. The brief calls for a low gate count, power efficient, mature processor, with a familiar, commercial-grade software development environment that can produce die-saving compact code. The design must be suitable for easy deployment (at full speed) in FPGA and in ASIC/ASSP and it must have a legal framework compatible with our business of licensing IP.
The RISC-V core we selected hits the scales at 20Kgates, punching at a respectable 2.44 Coremark/MHz, fitting the hardware checklist perfectly. Our internal bench-marking of performance and code compactness compared very favorably to best-in-class processors of similar size. Equally important, our experience shows that the effort to port a complete system to RISC-V is very low. Considering the more complex Wi-Fi platform as an example, it only took one week to integrate, simulate and build a new FPGA binary for our complete RivieraWaves Wi-Fi IP demo platform, with an embedded RISC-V processor replacing a commercial processor. Furthermore, the existing protocol software, which has been developed and deployed on multiple different commercial processors over the years, was ported over to the RISC-V platform within two weeks, with little to no fuss, thanks to the familiar GNU GCC/GDB and LLVM compiler/debugger environment. This effort included porting, testing and system level validation.
Overall, the project was a success and RISC-V truly delivered on its promise.