IAR Systems and Andes Join Forces to Improve RISC-V Performance
November 30, 2018
IAR Systems and Andes have come together to deliver powerful development tools for Andes? RISC-V-based solutions.
IAR Systems contributes the C/C++ compiler and debugger toolchain IAR Embedded Workbench, which offers leading code performance for size and speed, as well as extensive debug functionality.
Andes provides the RISC-V cores for a large gamut of applications including satellite navigation, high-precision sensor fusion, advanced smart meters, smart wireless communication, networking, voice processing, ADAS, storage, and machine/deep learning.
Andes and IAR Systems plan to support the cores in IAR Embedded Workbench in an effort to improve target applications’ functionality and warrant code density.
“Andes is moving heavily into RISC-V, and we are determined to support their efforts,” said Anders Holmberg, IAR Systems’ Chief Strategy Officer. “By providing maximized code speed and minimized code size for Andes’ powerful RISC-V cores, we will create new possibilities to reduce time to market and ensure high quality applications based on Andes’ RISC-V ISA.”
“We are excited to partner with IAR Systems to bring new capabilities to the RISC-V community,” said Dr. Charlie Su, Andes Technology Corporation’s CTO and Senior VP. “Together, we will offer powerful solutions for Andes V5 extended ISA as well as ACE that will enable our customers to meet the demanding requirements of today’s electronic devices.”