Embedded Insiders Open Up on RISC-V Summit, MIPI Debug & Trace Specs

By Perry Cohen

Associate Editor

Embedded Computing Design

December 19, 2019

The Insiders attended the second annual RISC-V Summit in San Jose earlier this month, and brought back some significant opinions about the show, the technology, and the direction of the Foundation.

The Insiders attended the second annual RISC-V Summit in San Jose earlier this month, and brought back some significant opinions about the show, the technology, and the direction of the RISC-V Foundation.

  • Is SiFive too powerful? 
  • Where are all the big semis? 
  • How does open hardware relate to Amazon, Apple, Google, and other tech giants building their own chips? And what does that mean for other chipmakers?

This episode also includes an interview with Enrico Carrieri, Chair of the MIPI Debug Working Group and Principal Engineer of Debug Architecture at Intel. Enrico puts his MIPI Alliance hat on to discuss the public availability of nine debug and trace specifications, which can be accessed directly from mipi.org. He also explains the importance of ecosystem enablement in the “necessary evil” world of debugging, and how new standards and tools can bring costs to a minimum.

Finally, a new segment with Jean Labrosse, Architect of the µC/OS RTOS, identifies “Things That Annoy a Veteran Software Engineer.” This week, he sounds off on following organizational coding standards.

Tune in.

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Perry Cohen, associate editor for Embedded Computing Design, is responsible for web content editing and creation, podcast production, and social media efforts. Perry has been published on both local and national news platforms including KTAR.com (Phoenix), ArizonaSports.com (Phoenix), AZFamily.com, Cronkite News, and MLB/MiLB among others. Perry received a BA in Journalism from the Walter Cronkite School of Journalism and Mass Communications at Arizona State university.

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