Efinix Announces Availability of Three RISC-V SoCs

By Tiera Oliver

Associate Editor

Embedded Computing Design

June 02, 2020

News

Efinix Announces Availability of Three RISC-V SoCs

Efinix announced availability of a series of three software defined, SoCs based on the RISC-V core. The Ruby, Jade, and Opal SoCs.

Efinix announced availability of a series of three software defined, SoCs based on the RISC-V core, Ruby, Jade, and Opal.

The three designs have been optimized for Efinix's Trion family of FPGAs and provide compute and I/O capabilities in devices from the T8 to the T120.

The SoCs are preconfigured with a RISC-V core, memory, a range of I/O, and have interfaces for embedding user functions. In this way, designers can create entire systems that include embedded compute and user defined accelerators within the same FPGA.

Efinix RISC-V SoCs come with a complete set of tools for compiling and debugging application code on the RISC-V core along with example applications and tutorials. They are compatible with the entire suite of Efinix development and evaluation boards and can be instantiated using the standard Efinity tool flow.

For more information, visit http://www.efinixinc.com.

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Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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