Andes, INVECAS Partner on Advanced-process RISC-V SoCs
December 01, 2018
Andes Technology and INVECAS are partnering to design SoCs based on RISC-V IP on advanced fab process technology, including 7nm, 14nm, 16nm, 22nm FDX, and 28nm HPC.
SAN JOSE. Andes Technology and INVECAS are partnering to design SoCs based on RISC-V IP on advanced fab process technology, including 7nm, 14nm, 16nm, 22nm FDX, and 28nm HPC. The collaboration will pair INVECAS’ front- and back-end SoC design expertise with Andes’ RISC-V IP offerings, including the A25/AX25, N25/N25F, and NX25/NX25F 32- and 64-bit CPU IP cores.
“INVECAS will leverage its design expertise with Andes’ new RISC-V IP Cores to provide a fast-track for SoC design teams wanting to implement the open-source RISC-V IP core without the delay of coming up to speed on this new open-source CPU instruction set architecture,” says Taher Madraswala, EVP and GM of INVECAS. “INVECAS has already implemented the Andes CPU IP cores for control on test shuttles in the most advanced process nodes. We also look forward to development of platforms for vertical markets in the near future.”
The ultimate goal of the partnership is to extend 64-bit RISC-V technology into applications such as AI and deep learning, as well as market segments like IoT, automotive, bio-medical, and hand-held devices.