Collaboration between RISC-V International and CHIPS Alliance Announced
April 06, 2021
RISC-V International and CHIPS Alliance announced a collaboration to update the OmniXtend Cache Coherency specification and protocol, along with building out developer tools for OmniXtend.
RISC-V International and CHIPS Alliance have formed a new OmniXtend working group which will focus on creating an open, cache coherent, unified memory standard for multicore compute architectures. The group will:
- Update the OmniXtend specification and protocol.
- Build out architectural simulation models.
- Reference register-transfer level (RTL) implementation.
- Create a verification workbench.
These tools for an open, standard unified memory coherency bus leveraging OmniXtend will make it easier for designers to take advantage of OmniXtend for data-centric applications.
For more information, visit riscv.org