Spirent and Synopsys Collaborate to Accelerate the Silicon Development Time to Market
September 01, 2021
New Networking SoC Test Solution Bridges the Gap Between Pre-Silicon and Post-Silicon Verification
The Spirent Chip Design Verification Solution speeds up the entire silicon development lifecycle and delivers significant cost savings by identifying and addressing issues in the IC design phase and before manufacturing starts. Combining network testing technology from an Ethernet test company with an emulation system provides more accurate and faster verification for Ethernet SoCs.
Spirent’s TestCenter platform is a networking traffic generator providing automated, scalable, and accurate Ethernet test patterns, which are a necessity for networking ASIC and SoC verification engineers. It is integrated with Synopsys ZeBu® Server, an emulation system, enabling pre-silicon SoC validation from 1G to 800G. The integration between the traffic generator and ZeBu Server is time-synced, which allows Layer 2-3 traffic generation and real-time results analysis.
Using the Spirent Chip Design Verification Solution in all phases of the chipset ecosystem provides:
- Improved operational efficiency and flexibility using virtualized testbeds
- Automation and reusability of test configurations between pre- and post-silicon teams
For more information, visit Spirent.