Smart High Level Synthesis (HLS) Tool Suite Enables C++ Based Algorithm Development Using Microchip’s PolarFire® FPGA Platform
September 01, 2021
The need to combine performance with low power consumption in edge compute applications has driven demand for Field Programmable Gate Arrays (FPGAs) to be used as power-efficient accelerators while also providing flexibility and speeding time to market. However, a large majority of edge compute, computer vision, and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware.
To enable this development community, Microchip Technology Inc. has added an HLS design workflow called SmartHLS to its PolarFire FPGA families that greatly enhances productivity and ease of design by allowing C++ algorithms to be directly translated to FPGA-optimized Register Transfer Level (RTL) code.
Based on the open-source Eclipse integrated development environment, the SmartHLS design suite uses C++ software code to generate an HDL IP component for integration into Microchip’s Libero SmartDesign projects. This enables engineers to describe hardware behavior at a level of abstraction not possible with traditional FPGA RTL tools. It further improves productivity while reducing development time through a multi-threading Application Programming Interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism as compared to other HLS offerings.
The SmartHLS tool requires up to 10 times fewer lines of code than an equivalent RTL design, with the resultant code being easier to read, understand, test, debug, and verify. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to now be used with PolarFire FPGAs and FPGA SoCs.
For more information, visit Microchip.