Watch Your Circuit's Input Voltage During Power-Up!

July 29, 2019


Watch Your Circuit's Input Voltage During Power-Up!

This blog points out a common EOS power-up condition with a simple added resistor solution.

Electrical overstress, or EOS, describes the damage to an electrical device that is caused by a current or voltage that goes beyond the device’s specification limits. But let’s get to the bottom line. Thermal damage manifests itself as visibly melted or burnt metal, carbonized mold compound, and other signs of heat damage such as metal lines and melted or vaporized bond wires.

Electrically, the device exhibits a catastrophic failure in multiple ways: sourcing or sinking excess supply current, appearing as a low resistance between the supply voltage and ground, shorted input or output pins to supply or ground, or open connections to one or more pins, and in most cases, a functional failure. An EOS event can be short-lived, lasting only milliseconds or can last as long as the out-of-specification condition persists. EOS can result from a single nonrecurring event or be the result of ongoing periodic or non-periodic events.

In a previous blog, “Using ESD circuitry for all your woes? Buyer beware!” we learned that EMI signals interfered and created havoc with a simple operational amplifier (op-amp). In this system, the combination of a circuit signal added to an injected EMI event pushed the device’s input stage beyond the power-supply specifications.

Another application scenario for an EOS event is when the op-amp’s input signal precedes the power-supply voltage. The buffer-configured amplifier is vulnerable to this sequence of power-up events (Figure 1).

Figure 1. A Single-supply amplifier in a buffer configuration.

Take a look at Figure 1 and imagine that the board’s input resistance is zero ohms. The input voltage (VIN) and subsequent current (IIN) goes through the signal’s very small source resistance (RS) and then goes directly into the noninverting input of the op-amp. In the theoretical amplifier buffer configuration, the amplifier output voltage (VOUT) will match the amplifier input voltage. In practice, the power-supply voltage is late to the game, and the amplifier’s slew rate will slow down this process.

This scenario can potentially damage the input ESD protection internal transistors if the current from the input source through the amplifier remains unchecked. For instance, imagine the supply is slowly ramped from 0 to 5V in 50ms, while the 3.5V input signal is applied 5ms after the supply begins its ramp (Figure 2).

Figure 2. A timing diagram for a potentially bad EOS event.

In Figure 2, the problem with this scenario is that the inputs are initially higher than the positive rail voltage. This high voltage turns on the amplifier’s positive ESD diode with an initial current spike greater than 30mA. Following the current spike, the current slowly decays from approximately 17.5mA to 0mA. This decay continues until the voltage difference between the supply and input is somewhat less than 0.6V. If the input source (VIN) has a low impedance (RS) and can deliver the current, then a potentially harmful current flows through the IC traces, ESD diode, and bond wires.

This beautiful simulation points out the problem; however, in real life, your amplifier’s traces and junctions are destroyed. So, let’s solve this problem. By including the 10kW to 100kW series input resistor (RIN), it will protect the input circuit from damage. With the input series resistor, the voltage to the amplifier’s input will be reduced by RIN x IIN.

EOS induces thermal damage to components under an over-voltage, over-current condition. Presently, there is no industry testing standard for EOS conditions. To keep yourself out of EOS trouble, control your power supply ramps and monitor the conditions of I/O pins during the power-up and power-down activity. And as we learned in the previous blog, shield sensitive high-impedance traces from EMI occurrences. This blog points out a common EOS power-up condition with a simple added resistor solution.  

Analog & Power