The Engineer's Answer to Faster Sampling at Lower Power

By Joao Marques

Engineering Design Centre Manager

Adesto Technologies Corporation

December 02, 2019


The Engineer's Answer to Faster Sampling at Lower Power

We live in an analog world, despite the dominance of digital technology. Moving between domains introduces quantization errors; it is inevitable.

We live in an analog world, despite the dominance of digital technology. Moving between domains introduces quantization errors; it is inevitable. The engineer's job is to make that transition as seamless as possible, which is where the ADC and DAC come in.

Analog-to-digital conversion (ADC), can take many forms and come with many compromises. Fundamentally, the key figures of merit are accuracy and speed. To complicate things, these two parameters are normally opposing; higher accuracy requires more bits, but adding more bits reduces the sampling rate. Faster conversion typically comes at the cost of the effective number of bits. In very broad terms, the choice is book-ended by the Delta-Sigma conversion topology (high resolution, long latency) or the Flash converter (high speed, but at the cost of power and area). Sitting in between these two extremes is the Successive Approximation Register, or SAR converter. This 'goldilocks' technology offers a good compromise between resolution and speed, but it too has its limitations.

In general, SAR converters have been a good choice in analog front ends (AFEs) as used in wireless communication, thanks to their mix of accuracy and speed. As the IoT's reach extends further from the core, pushing the edge forever outwards, there is growing demand for AFEs that can handle more complex protocols at higher frequencies (and consequently higher sampling rates), but at lower power. Let's not call this a problem, rather let's call it an opportunity, to find a technology that can enable smaller, faster and lower power AFEs in an era when wireless connectivity needs to fit into something small enough to wear in an ear, and potentially be powered from energy harvested from its operating environment.

A little background on the SAR

As the name suggests, a SAR operates by successively approximating the value of the analog input, iteratively comparing the input voltage to a reference that is repeatedly halved until the difference between the reference and the source is either indistinguishable or meets the design's requirements. Each comparison generates a 'higher' or 'lower' result which forms one bit in the digital output, starting with the most significant bit. This continues until the converter generates enough bits to represent the analog input, with enough accuracy.

Figure 1: An example of a 3-bit SAR ADC

As all of the steps need to be completed within the sampling period, the number of bits possible will predominantly be determined by the response time of the elements in the circuit that need to change. This includes the reference voltage used in the comparison with the input voltage (typically stored in a sample-and-hold circuit comprising a switch and capacitor). In turn, this reference voltage is (normally) generated by a digital-to analog converter, or DAC. It follows, then, that the sampling rate of a SAR converter will be determined to some extent by the DAC used to generate the reference voltage and the control logic, but in general SAR performance is actually limited by the speed of the comparator. The switched capacitor at the input, which is effectively a low-pass filter, introduces an upper frequency threshold, but as the switch will have a low resistance and the capacitor will be small, this means the converter can generally handle signals of hundreds of MHz or higher; another positive feature of the SAR.

In terms of overall accuracy and not just resolution, it is important that the reference voltage generated for use by the DAC (rather than the DAC-generated voltage for the comparator) is also as accurate as possible, as all other measurements will be relative to this. SARs that integrate as much of the total solution as possible, including the switched capacitor S&H and DAC reference voltage generator, will deliver the best performance.

Overcoming the limitations of SAR converters

A Pipelined ADC features multiple stages that each handle part of the conversion process. As each stage completes its operation it becomes free to accept the next sample. One of the main benefits offered by a pipelined ADC is its speed; once the pipeline is fully primed it can generate a new output as new samples 'push' the data along. While a SAR's architecture is normally based on single stage used multiple times, a Pipelined converter uses parallelism to speed things up.

Combining the SAR and Pipelined approaches results in the so-called SAR-Assisted Pipelined ADC. Adesto's engineers have implemented this approach to create an ADC that can operate at high bandwidths with maximum speed and accuracy, yet requires minimal power and area.

The converter developed by Adesto uses two SAR stages; the first stage handles the most-significant bits of the output, while the second stage handles the least-significant bits. By adding a digital block to take care of the timing and correction (see Figure 2), the SAR-assisted pipeline converter can generate a result in less than half the time it would take a comparable SAR converter, without the penalties associated with a conventional pipelined ADC (which include physical size and power consumption).

Figure 2: The SAR-Assisted Pipeline ADC architecture

In simple terms, as soon as the first SAR stage has completed its conversion it can accept a new sample, while the second SAR stage finishes the conversion of the first sample. The gain of the amplifier between the stages relaxes the requirements for the second SAR, resulting in a solution even more energy-efficient than the SAR itself.

Figure 3 shows a block diagram of Adesto's SAR-Assisted Pipeline ADC.

Figure 3: Adesto's single-channel SAR-Assisted Pipeline ADC

As can be seen in Figure 3, the IP developed by Adesto incorporates all of the critical functions, including the reference voltage generator, the timing and control logic, and digital calibration, as well as decoupling capacitors. The use of deep n-well technology for all the analog blocks provides immunity to substrate noise, which is particularly important when the IP is licensed for use by a customer in a design that may not have a dedicated analog supply available. The design is truly comprehensive, as it requires no external voltage references or regulators.

The same core IP has been used to develop a dual-channel solution aimed at quadrature I/Q modulation architectures (Figure 4). As can be seen, some of the functionality can be shared across both channels, while separate reference buffers and clock trees are included in order to minimize crosstalk between the channels.

Figure 4: Adesto's dual-channel SAR-Assisted Pipeline ADC

One of the key benefits offered by this approach is its low power operation. Adesto deployed in volume IP that is available now, including a dual-channel solution in a 28nm process that delivers 160Msamples/s on each channel with a total power dissipation of just 18mW. The die area in total for this ADC is just 0.055mm2, making it extremely area-efficient. Despite this level of integration, it can deliver a SNDR of 63.1dB and the crosstalk between channels is below -80.0dB.

An eight-channel version of the same converter can handle four I/Q channels simultaneously, operating at 122.88Msamples/s while still only dissipating 45mW. It has an effective number of bits (ENOB) of 10.2-bits, yet still only requires a die area of 0.3mm2. Adesto can also offer a 12-bit SAR-Assisted Pipeline ADC that achieves a sample rate of 200Msamples/s, dissipating 10mW, in a die area of just 0.05mm2.

AFEs rely heavily on the performance of the ADC, and the humble SAR is one of the most reliable and versatile architectures available to engineers. This is just one example of the IP available from Adesto that has been optimized to meet the demands made by the latest applications.

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Joao Marques is the Director and Group Manager of Adesto’s Portuguese site, where he leads the development of high-performance, low-power mixed-signal circuits design, with focus on data converters. He has been involved in a large number of successful designs, including IP and ASIC products. He has over twenty years’ experience in the semiconductor industry and he has held various technical and management positions. He holds one U.S. patent on data converters. Before Adesto Technologies, he worked in companies including Chipidea Microelectronics (now Synopsys), Integration Associates Inc., Silicon Laboratories Inc. and S3 Group. He holds a degree in Electrical Engineering and Computer Science from the Instituto Superior Tecnico, Lisbon, Portugal.

Analog & Power