Setup Violation Fixing in Timing Critical Complex Designs Using Late Clocking
September 22, 2020
Now a days the performance of these chips and clock frequencies are going higher and higher to meet the high-speed data traffic over the internet, or intensive CPU tasks itself.
The integrated circuits are the heart of any electronic device. Now a days the performance of these chips and clock frequencies are going higher and higher to meet the high-speed data traffic over the internet, or intensive CPU tasks itself. Timing/Speed is the most important aspect of these devices and companies are pushing themselves to meet this high performance targets in a shorter period. Thus, timing/signoff is a very crucial, critical stage for addressing the high throughput requirement of ASIC chip design to decide the overall time to market.
There are various EDA tools available to do timing analysis and timing fixes through data path optimization. But, the main focus of this article is to provide insights/algorithms of remaining setup timing fixes using late clocking technique without impacting the other matrix of timing analysis.
The Fundamental Approach to fix Setup violation
Setup violation occurs when data-path is slowly compared to the clock captured at capture flop. With this thing in mind, various approaches are there to fix the setup.
Data path optimization
There are many ways to fix optimized data paths like Upsize, vtswap, and insert buffer-repeater in data-path, etc. This can be achieved using the signoff tool’s eco generation feature. After running one round of timing fix, the signoff timing tool already applies all possible data-path optimization techniques. It cannot fix the remaining violation by further optimization in data-path either it might cause quality degradation in other paths or no further scope to optimize data-paths.
Using useful skew
To fix the remaining setup violations, we have no choice but to fix paths in signoff tool.
Touching clock path is one of the solutions, here.
If data-path is pretty much optimized, then the last option remains to fix the setup violation is to use “useful skew” concept. Useful skew involves two methods: early clock and late clock. Either reduces the launch clock delay or increase capture clock delay. However, to change the clock, one has to make sure that upstream, for early clock, and downstream, for late clock, paths are not violating.
Early Launch clock
Earlier clocking requires checking physical net/cell location in PnR implementation tool and then decide proper candidates for the early clock. Also to implement the early clock eco in signoff tool, extracted r/c will differ by bigger amount for the new net. Thus, early clocking causes maximum impact in RC between implementation and the signoff tool. To implement an early clock, apart from physical changes, logical changes like disconnect/connect is used, so always run formality.
Late Capture clock
For late clock, newly added clock cells will be placed near to capture flop, and net-length for newly created net will be very smaller. Thus, R/C extraction data still valid as impact of change in RC value is minimal. It is better to create eco using “Late clocking” method.
Why We focused on late clocking instead of early clock
As mentioned earlier, late clocking causes minimal impact in RC correlation between eco implementation tool, and signoff timing tools. If there are multiple paths converging at same endpoint, it is easy to separate paths based on endpoint and apply setup fix on endpoint, can fix majority of setup paths.
Multi-scenario analysis feature can provide ease to check setup/hold violation in same session.
We followed below algorithm to create setup eco using late clocking.
It requires one-time effort to incorporate the above flowchart steps into script. Once the script is generated, it reduces total time to analyze all paths and generate timing eco.
We were able to deploy all steps in the above algorithm and ran it on a design with deep submicron technology. Script can analyze all setup paths and creates two output files. 1. summary.csv and 2. late_clock_eco.tcl
Consider scenario of Image-2 where Setup is violated from UFF0/CK to FFF1/D. [Sample output is shown below].
For designs having setup/hold, violating across multiple scenarios. Interested setup/hold scenarios can be loaded in the signoff tool and script can generate eco without disturbing non violated setup/hold paths.
If next-cycle setup is violated, script will not add any buffer on UFF1/CK. Similarly, if hold is violated on UFF1/D, script will not add any buffer on UFF1/CK.
After increasing setup margin for next cycle path [UFF1/CK to UFF2/D], increasing hold margin for same cycle[UFF1/D], and running script will add buffer.
The above flow/script is used on one block to fix setup violations. Before using this script, the below assumptions were made :
- Reference block is taken having moderate congestion in PnR. For highly congested design , tight routing resource or highly utilized design will have no adequate space for eco implementation.
- Correlation between implementation/PNR Tool and signoff Timing tool is proper.
- STA engineer has understanding of back end implementation tool and able to debug if got any issue to implement eco.
Below is design complexity:
- Technology: deep sub-micron
- placed cells count (Approximately) : 1100 K
- Utilization (stdcell-row / total): 40%/50%
- Total added late clock cells: 7250
Further addition in above algorithm
For complex, high-speed designs, target insertion delay/max latency is crucial. Restrictions are not to exceed the max latency while fixing timing violation. This special case can also be added in the above algorithm.
STA analysis is becoming more important, and a crucial domain for addressing high throughput requirement of high performance computing, advanced graphics and network SOC to decide overall time to market in today’s challenging lower node technology era. New algorithms and scripts are created to fix setup/hold timing issues. It will help to reduce Timing signoff closure and consequently reducing time to market. Even after data path is optimized completely, with using late clocking for useful skew is really helping for faster and accurate timing closure without any manually efforts.
About the Author
Jignesh Patel is a Technical Lead at eInfochips – an Arrow Company. He holds a Bachelor of Technology degree in Electronics and Communication from Nirma University, Ahmedabad, Gujarat. He possesses over 7 years of experience in ASIC Physical Design and worked on various technologies from 90nm to 7nm and has done successful taped out from RTL netlist to GDS. he has developed expertise in PnR Implementation, static timing analysis and other Signoff activities.