Mentor Introduces AI/ML Toolkit, Adds AI/ML Power to Calibre Tools
July 11, 2019
Mentor is releasing an AI/machine learning development kit and added AI/ML enhancements to two tools to help its customers produce smarter, AI/ML-powered ICs to market faster.
As I mentioned recently, if you’re not talking about artificial intelligence (AI), you may find yourself out of the conversation. Mentor, a Siemens business, is putting itself squarely in the center of the conversation by releasing an AI/machine learning development kit and added AI/ML enhancements to two tools to help its customers produce smarter, AI/ML-powered ICs to market faster.
The company’s Catapult software high-level synthesis (HLS) toolkit and ecosystem are designed to help customers jumpstart the development of complex machine learning IC architectures. Simultaneously, Mentor is adding AI/ML infrastructure throughout the Calibre platform, and is launching the first two of these AI/ML-powered technologies, namely Calibre Machine Learning OPC (mlOPC) and LFD with Machine Learning. Both technologies leverage machine learning software for faster, more accurate results.
The Catapult HLS AI toolkit helps developers on their AI/ML-based accelerators for edge applications. Based in HLS C++, the kit provides an object detection reference design and IP to help designers quickly find optimal power, performance and area implementations for neural network accelerator engines. The solution also includes a complete setup to build an AI/ML demonstrator platform, with live HDMI feed on an FPGA prototyping board.
According to the company, the new Calibre mlOPC product provides 3X faster OPC run time compared to prior tools. It does this through intelligent feature extraction and machine learning algorithms to predict the OPC output to within a nanometer of accuracy, eliminating up to 75 percent of OPC run time.
Mentor has also added a machine learning option for its lithography simulation tool. The new feature is engineered for high accuracy and improved performance on large blocks as well as full-chip analysis. The feature’s predictive capability focuses on high-risk layout patterns for detailed lithography simulation, removing low-risk patterns from this compute-intensive step. The result is a 10 to 20x performance improvement over full chip-model based simulation while maintaining optimal accuracy.