Yole Report Identifies AI, HPC as Key Drivers of 2.5D, 3D TSV tech
February 07, 2019
According to 2.5D / 3D TSV & Wafer Level Stacking: Technology & Market Updates, the stacking technologies market is expected to grow at a CAGR of 27 percent to more than $5.5 billion in 2023.
LYON, France. A report by Yole Development suggests that 2.5D and 3D Through-Silicon Via (TSV) technology is being driven by applications such as artificial intelligence and high-performance computing (HPC). The report, “2.5D / 3D TSV & Wafer Level Stacking: Technology & Market Updates,” highlights TSVs, 3D SoCs, and hybrid bonding packaging techniques used in hardware like 3D stacked memory, GPUs, FPGAs, and CMOS image sensors.
According to the report, “2.5D / 3D TSV & Wafer Level Stacking: Technology & Market Updates,” the stacking technologies market is expected to grow at a CAGR of 27 percent to more than $5.5 billion in 2023. HPC use of TSV and other stacking technologies is expected to double over this period, from 20 percent of total market share in 2018 to 40 percent at the end of the sample period. This represents roughly 6x growth from current market size.
The report also covers emerging TSV-less technologies, categorized as “with substrate” and “embedded in substrate” solutions. With-substrate technologies are currently used in Apple processors, while alternatives like the RDL11 interposer technology are scheduled to hit the market in 2020.
Companies covered in the report include Alchip, Alibaba, Amazon, AMD, Amkor, AMS, Apple, Audi, Avago, Baidu, Bosch, Bitmain, Broadcom, Cisco, DARPA, Facebook, Faraday, Foxconn and others.
A sample of the report can be viewed here: https://www.i-micronews.com/images/SAMPLES/PACKAGING/2.5D_3D_TSV_and_Wafer-Level_Stacking_Technology_and_Market_Sample.pdf.