Imperas to present RISC-V processor verification tutorial at DVCon Europe in collaboration with Google and Metrics

November 05, 2019

Press Release

Imperas to present RISC-V processor verification tutorial at DVCon Europe in collaboration with Google and Metrics

Tutorial to address RISC-V compliance and verification techniques for processor cores including optional custom extensions.

Oxford, United Kingdom, October 21, 2019 - Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, will co-present a tutorial at the 2019 Design and Verification Conference and Exhibition (DVCon Europe) on the latest development in verification and compliance testing for RISC-V open ISA processors along with partners Google Inc. and Metrics Technologies Inc.

Compliance testing has become mission-critical for the RISC-V ecosystem to accommodate the wide adoption and support of compatible features whilst retaining the optimizations that the open ISA permits. This session will introduce the methodologies being developed for compliance and verification testing of RISC-V, including a framework for development of additional tests, the development of the tests, reference models and configurations for the RISC-V specification subsets. It will cover RISC-V compliance testing and verification with the open source RISC-V instruction stream generator developed by Google, the Imperas reference simulator and models, together with the Metrics cloud-based testing infrastructure and scalable capacity flexibility.

DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. It takes place at the Holiday Inn, Munich City centre on October 29th-30th.  For more information or to meet with Imperas to discuss virtual platforms for embedded software and systems development, debug and test at DVCon Europe please get in touch here.

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