OneSpin's Newest App Assures Quality of RISC-V Processor Cores for Safety-, Security-Critical Applications

July 29, 2019


OneSpin's Newest App Assures Quality of RISC-V Processor Cores for Safety-, Security-Critical Applications

RISC-V Verification App Provides RISC-V Community with Only Solution to Exhaustively Verify IP Implementations, Ensure 100% Compliance.

OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits, today unveiled the formal RISC-V Verification™ App, the first App in the OneSpin RISC-V Integrity™ Verification Solution for safety- and security-critical applications.

"RISC-V is shaking up the established IP and semiconductor ecosystems," observes Sven Beyer, product manager, design verification at OneSpin, a member of the RISC-V Foundation. "Effective third-party verification solutions are essential for both RISC-V core providers and SoC integrators to realize the full potential of this architecture. Our proven solution is the only choice for efficient and complete verification, providing the RISC-V community the much-needed tool for assuring IC integrity."

Increasing demand for the RISC-V open-source architecture underscores the importance in establishing high quality in processor cores. The complex architecture provides many configuration options, enables a wide range of micro-architectures and allows the addition of custom extensions. This results in difficult verification challenges.

OneSpin's App provides the growing RISC-V community with the only means to exhaustively verify that these cores are developed and integrated with zero bug escapes and guarantee full compliance with the Instruction Set Architecture (ISA). It enables core providers to compete with older, established instruction set architectures and add value to their designs without compromising compliance.

Its automated solution needs only a few days to set up and only two hours to run on a complete core, shaving months off verification schedules. Other verification approaches are inadequate and fall short of delivering complete results. Simulation can take months to set up followed by weeks of regression runs only to miss critical bugs. Other formal methods use only bounded proofs and therefore are unable to detect hidden functionality, leading to incomplete verification.

OneSpin's RISC-V Verification App

The App is part of the recently announced OneSpin RISC-V Integrity Verification Solution. It meets the verification challenges of RISC-V cores by capturing and verifying implementation choices, such as microarchitecture and ISA options.

It identifies unspecified instructions and control and status registers (CSRs), captures and verifies custom extensions allowed by RISC-V and formally verifies core compliance to the ISA, captured by a set of SystemVerilog Assertions (SVA). The App finds all compliance-related bugs. Once bugs are fixed, the App proves 100% compliance. Setup takes less than a week and requires two hours to run on a complete core.

OneSpin's RISC-V Verification App has been proven by running on available open-source RISC-V cores. For example, the App found multiple bugs in Rocket Core confirmed by developers and fixed in the open-source repository. Reference: "Complete Formal Verification of RISC-V Processor IPs for Trojan-Free Trusted ICs" by Paul McHale (Edaptive Computing) and David Landoll, GOMACTech Conference.

In a separate news release today, OneSpin announced its OneSpin 360 EC-FPGA now supports three Intel® field programmable gate array (FPGA) families. They are Cyclone® V using Intel Quartus® Prime Standard Edition software for synthesis and place-and-route, and Stratix® 10 and Arria® 10 with Intel Quartus® Prime Pro Edition software for synthesis and place-and-route.

Availability and Pricing

The RISC-V Verification App is shipping now, as is the latest version of OneSpin 360 EC-FPGA.

Pricing is available upon request.

OneSpin at DAC

The RISC-V Verification App, EC-FPGA and OneSpin's other certified IC integrity verification solutions will be featured at the 56th Design Automation Conference (DAC) in Booth #308 Monday-Wednesday, June 3-5, from 10 a.m. until 6 p.m. at the Las Vegas Convention Center.

DAC attendees can schedule demonstrations by visiting

OneSpin will host "Verified," the annual celebration of the verification ecosystem, at Topgolf Las Vegas at MGM Grand Monday, June 3, during DAC. A limited number of tickets is available from OneSpin or its co-hosts Agnisys, AMIQ EDA, Avery Design Systems, Blue Pearl Software, Breker Verification Systems, Concept Engineering, Dassault Systèmes, Imperas, Semifore and Verific Design Automation.

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