Achronix to demonstrate embedded FPGA solutions at Design Automation Conference

June 19, 2018

Press Release

Achronix to demonstrate embedded FPGA solutions at Design Automation Conference

Will Profile Speedcore eFPGA IP's ability to add a programmable fabric to ASIC or SoC Designs Two IP Track Talks will feature presentations from Achronix's Steve Mensor, Kent Orthner

WHO: Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP)

WHAT: Will exhibit at the Design Automation Conference (DAC) in Booth #2463, showcasing Speedcore eFPGA IP for 5G wireless, high-performance computing (HPC), advanced driver assistance systems (ADAS) and autonomous vehicles, machine learning and computer vision. Achronix will demonstrate how Speedcore’s eFPGA programmable fabric can be implemented into an ASIC or SoC for a more flexible solution.

WHEN: Monday, June 25, through Wednesday, June 27, from 10 a.m. until 6 p.m.

WHERE: Moscone Center West, San Francisco

Achronix executives will deliver talks during two DAC IP Track sessions:

Steve Mensor, Achronix’s vice president of marketing, will present “Increase Performance, Reduce Die Size with Speedcore eFPGA Custom Blocks Flow,” during “Has the Time for Embedded FPGA Come at Last?” It will be held Tuesday from 1:30 p.m. until 3:30 p.m.

Kent Orthner, Achronix system architect, will present “Learning to Share –– Embedded FPGA Timing Closure,” part of the “New Challenges for IP and VIP to Support Emerging Application or Algorithm” session Tuesday from 3:30 p.m. to 5 p.m.

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