Andes RISC-V Cores add Hex Five TEE to GOWIN FPGAs
December 01, 2018
The MultiZone Security TEE provides policy-based, hardware-enforced separation for unlimited security zones, as well as full control over data, code, interrupts, and peripherals.
SAN JOSE. A collaboration between Andes Technology, GOWIN Semiconductor, Hex Five Security has enabled the MultiZone Security Trusted Execution Environment (TEE) on Andes’ N(X)25 RISC-V cores integrated in GOWIN GW-2A family of FPGAs.
The MultiZone Security TEE provides policy-based, hardware-enforced separation for unlimited security zones, as well as full control over data, code, interrupts, and peripherals. Using the MultiZone Configurator, fully compiled and linked code is merged with the Hex Five nanoKernel without any changes to hardware or customer code bases.
GOWIN’s GW2A devices are the first FPGAs with embedded pSRAM, and include abundant logic, high-performance DSP resources, and high-speed I/O. Andes 32-bit N25(F)/A25 and 64-bit NX25(F)/AX25 RISC-V-compliant CPU cores on the GOWIN FPGAs support user and machine mode, with the A25/AX25 also supporting supervisor mode and an MMU for the Linux kernel and applications.
“With MultiZone Security, [customers] can implement a robust security solution on our existing FPGAs without the need for new hardware, deep security expertise, or even any changes to their toolset and workflow,” says Jim Gao, Director of Solution Development, GOWIN Semiconductor. “This allows a customer to get to market fast, which is the goal of our FPGA solutions.”
For more information visit https://hex-five.com.