Cadence Design Tool Implements ML for More Effective Digital IC Design
August 02, 2021
When I first heard about this, it sounded like a little smoke and mirrors, to be able to work the latest buzzwords into the product’s announcement. But a deeper dive reveals that ML implementation is really taking place here.
According to the company, combining Cerebrus and Cadence’s RTL-to-signoff flow offers the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).
The list of benefits offered by Cerebrus includes:
- reinforcement ML, which quickly finds flow solutions humans might not naturally try or explore
- ML model reuse, which permits design learnings be automatically applied to future designs
- improved productivity by allowing the engineer to optimize the complete RTL-to-GDS flow automatically for many blocks concurrently
- massively distributed computing, which provides scalable on-premise or cloud-based designs, resulting in faster flow optimization
Cerebrus fits in well with the broader Cadence digital full flow, working seamlessly with the synthesis, timing, power, and verification tools for a complete design flow.
For more information, visit:www.cadence.com