Implementing PCI Express bridging solutions in an FPGA
May 01, 2010
A low-power FPGA can connect PCIe devices to previous-generation devices with a parallel bus.
One advantage of using FPGAs is the ability to implement proven intellectual property to complete bridging functions quickly and with confidence. A look at a common but complex interface, PCI Express, demonstrates these benefits.
Like its predecessor, the Peripheral Component Interconnect (PCI), PCI Express (PCIe) is becoming a ubiquitous system interface. Unlike PCI, PCIe adopts a SERDES interface to provide users with the scalability required for future applications. As system bandwidths increase, more applications are moving to SERDES-based interfaces like PCIe. In the past, Application-Specific ICs (ASICs) and Application-Specific Standard Products (ASSPs) were typically used to implement next-generation interface solutions. ASICs and ASSPs were popular choices because they provided a low-cost, low-power design solution.
However, several new FPGA families present attractive options for PCIe interfaces. FPGAs provide an adaptable platform without the the inflexibility of ASSPs or the long lead times and large nonrecurring engineering costs typically associated with ASICs. Newer-generation FPGAs with embedded SERDES offer designers an extremely rich, high-value programmable architecture in a low-cost, low-power solution for serial interfaces. The same FPGAs can be used to support a variety of serial protocols like PCIe, GbE, SGMII, XAUI, Serial RapidIO, and others, providing a single FPGA platform for multiple designs.
PCIe is also becoming the interface of choice for control plane applications, replacing older parallel interfaces like PCI. Newer-generation devices use one or more PCIe links. In a majority of devices, the PCIe core is implemented as a PCIe endpoint. Designers often need to connect these devices to previous-generation devices that have a parallel bus (such as microprocessors with parallel bus interfaces). Using a low-cost, low-power FPGA to bridge between PCIe and a parallel interface provides designers the flexibility to solve this problem without exceeding their system cost and power budgets.
As designers migrate from PCI to PCIe, the intricacies of the protocol coupled with the complexities involved with SERDES-based designs pose significant challenges. Fortunately, FPGAs combined with a full-featured PCIe IP core, reference designs, hardware evaluation boards, and associated demos help smooth out the otherwise steep learning curve PCIe designers face. FPGAs are an ideal platform for PCIe-based applications. Because they are programmable, FPGAs give designers the flexibility to resolve design issues late in the design cycle with rapid turnaround times. Designers can readily change or add features as individual design requirements evolve. FPGA designs also allow designers to make updates to accommodate changes to the specifications, enabling them to future-proof their designs against obsolescence. The programmable platform enables designers to use the same FPGA to implement interface solutions that connect to a broad variety of other PCIe chipsets: endpoints, root complex, or switches. The designer can integrate other functions required by the system in the FPGA, reducing the number of components on the board and further decreasing the total cost of the system.
FPGAs provide an extremely flexible programmable platform for system designs. A comprehensive solution package that includes IP cores, hardware platforms, demo designs, drivers, and software enables designers to shrink their development cycles while reducing the complexity of the design.
One common design requirement is for a PCIe solution to bridge between PCIe serial interfaces (endpoint devices) and legacy parallel bus interfaces, as shown in Figure 1. An FPGA with a PCIe root complex IP core provides designers with the basic building blocks needed to implement such a solution. Alternatively, ASSPs and ASICs can also implement this function. However, unlike FPGAs, these devices can implement only a fixed configuration that cannot be changed to accommodate the various parallel bus interfaces available.
A programmable FPGA platform, on the other hand, enables designers to make specific changes in their design to implement the specific bridge function that matches the interface available on their particular board. Designers also have the flexibility of implementing multiple bridges or different configurations of bridges in a single FPGA, thus reducing the total components on the board. An FPGA coupled with the PCIe root complex IP core can enable several other bridging solutions as required by a design.
PCIe root complex
A PCIe endpoint operates as an upstream device, a function that a root complex device can perform. However, a full-featured root complex implementation is quite expensive in terms of FPGA gates used. Instead, a lightweight root complex core with a subset of the transaction layer functionality is adequate for implementing most bridging functions.
As shown in Figure 1, the bridge comprises two basic building blocks. The first block is the PCIe root complex (or Root Complex-lite) IP core, which interfaces with the PCIe endpoint device. The second block is the bridge logic that interfaces to the local bus/parallel interface. Because this implementation is in a programmable FPGA, the designer has flexibility to customize the design based on specific interface needs. Other functionality can also be integrated into the same FPGA, eliminating other components on the board and reducing overall bill of materials costs.
Implementing lighter IP
PCIe is a complex protocol. Providing fully functional, fully validated PCIe IP cores significantly reduces design complexity. For example, Lattice Semiconductor’s PCIe Root Complex Lite (RC-lite) core implements a x1 or x4 root complex function primarily for use in PCIe bridging applications. As shown in Figure 2, all of the PCIe layers are implemented as a combination of embedded ASIC blocks and the PCIe RC-lite soft IP core implemented in the FPGA. The various blocks include the electrical SERDES interface, physical layer, data link layer, and a minimum transaction layer to support the protocol stacks required to implement a PCI Express root complex function. This lighter IP is optimized for use in simple bridging applications between a PCIe endpoint interface and a parallel local bus interface.
The PCIe RC-lite IP implemented in a LatticeECP2M or LatticeECP3 FPGA enables low-cost, low-power PCIe bridging applications while providing designers the flexibility to customize the bridge interface. Additionally, PCIe hardware evaluation boards and a variety of reference designs, demos, and software drivers help designers kick-start their PCIe designs and reduce time to market. Lattice also provides a hardware evaluation board for designers to test the RC-lite IP solution. Designers can complete interoperability and verify the system-level functionality of these solutions prior to deployment, saving the time and cost normally associated with post-design debug and performance enhancements.
Bridging complexity simplified
PCIe designs pose significant challenges to designers. The requirements for the interface are varied, depending on whether the PCIe device has to connect to another endpoint, root complex, or switch. Furthermore, designs often require a connection between a PCIe endpoint device and another device with a parallel bus interface.
Designers can implement these functions in a low-cost, low-power FPGA platform while retaining all the benefits of a flexible programmable architecture. Using a PCIe root complex IP function in an FPGA provides an ideal platform to implement these bridging functions.
Sidhartha Mohanty is a strategic marketing manager for Lattice Semiconductor. He holds a BE in Electrical and Electronics Engineering from BITS, Pilani, India; an MS in Computer Engineering from the University of Cincinnati; and an MBA from Lehigh University. Sidhartha has broad experience in the communications industry with AT&T, Lucent Technologies, Agere Systems, and Lattice.