Ethernet is widely used for all kinds of applications. However, for demanding multimedia-streaming applications in a fully loaded network, Ethernet is not the right choice due to its limited Quality-of-Service (QoS) support. The IEEE 802.1 Audio/Video Bridging (AVB) standard, an extension to legacy Ethernet, provides the QoS features needed for multimedia streaming, such as time-synchronized low-latency streaming services and bandwidth reservation. AVB replaces both the physical complexity of cables and the network complexity of earlier proprietary solutions with an open, standards-based approach that greatly simplifies network management and support.

System-level modeling of AVB-based systems provides greater visibility into the network architecture, node-to-node delay, and available bandwidth on channels and even helps in digging out potential challenges and bottlenecks in proposed system architectures. This also lets the user conduct a variety of analyses by changing traffic rate, traffic pattern, and routing between talkers and listeners to compute the throughput and network latency. Availability of these highly crucial system characteristics will enable the designer to define an optimal network architecture that meets user requirements.

My trade-off and analysis focuses on performance, power, and reliability. To facilitate this, I’ve constructed an event-driven timing simulation model using VisualSim Architect from Mirabilis Design. This model will be simulated by the designer to experiment with topologies, workload, and AVB configurations. In a simple example to illustrate usage the simulation model represents video recording and storage system. The video recorder is connected to an AVB node that is transmitted via an AVB switch to an AVB node hosting the solid-state recorder. In AVB terminology, the video recorder is the talker and recorder is the listener. The real system would involve hundreds of talkers and listeners. A VisualSim model of the proposed simple design is shown in Figure 1.

In the model, the camera module is a traffic generator. I used the VisualSim AVB library to assemble the network topology. The configurations were edited in a CSV files and provided to the simulation model. Example configurations include the routing table, bandwidth to type of service, Class A and B to type, and the traffic streams for each talker. The user will start with a VisualSim distribution-driven workload generation. If the designer has any trace files captured from the real hardware, then those can be used as source files. Simulation results to look for would be throughput, end-to-end latency, utilization, and network latency.

Bringing the real hardware device in loop with the VisualSim modeling flow provides more leverage toward system verification and test-case generation. One scenario, shown in Figure 2, interfaces VisualSim with a physical switch and a recorder device.

In this case, the AVB model in VisualSim will generate multiple streams from a single IP address. The latency at the Receiver is saved in a file during the system model run. When the model is running with the hardware-in-the-loop, the latency is compared with the expected latency from the system model.

Model-based system development for AVB-based systems eliminates the risk of product re-spin and increases the confidence for system designers on the selected architecture. At the early product-development stage, designers can inject faults to the simulation model to detect possible challenges that a system may encounter. Identifying all bottlenecks and resource limitations early in the design flow lets designers develop error-free systems and also eliminate the risk of product re-spins and also meet time-to-market requirements.

Ranjith K R is an EDA applications engineer, specializing in VisualSim system-level products at Mirabilis Design Inc. in Bengaluru, India. He has many years of expertise in system-level modeling, simulation, and development. Ranjith has been involved in various system-level model development projects with the defense and aerospace sectors, and multinational semiconductor companies in India. He completed his MS in Electronics from Kuvempu University and received a diploma in FPGA design and verification.