X-FAB, Efabless Release First Silicon of ?Raven? RISC-V SoC

June 13, 2019

X-FAB, Efabless Release First Silicon of ?Raven? RISC-V SoC

A mixed-signal SoC, nearly 75 percent of Raven?s die area leverages X-FAB analog IP and standard macros. Simulations project a maximum clock speed of 150 MHz.

X-FAB and Efabless Corporation have announced first-silicon availability of Raven, an open-source SoC reference design based on the PicoRV32 RISC-V core. A mixed-signal SoC, nearly 75 percent of Raven’s die area leverages X-FAB analog IP and standard macros. Simulations project a maximum clock speed of 150 MHz.

Raven was created using an open-source design flow in less than three months. The chip is being manufactured on X-FAB’s automotive-grade 180 nm, 6-metal process, and supports a variety of optional features. These include:

  • Low-power option
  • On-chip isolation for high voltages
  • High-temperature flash memory

The semiconductor design is fully functional. The license-free reference design is available on the Efabless marketplace. The company is also engaged with initial customers on derivative designs.

Further technical details on the Raven chip can be found on Github.

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