Imperas riscvOVPsim brings free, open-source modeling and simulation to RISC-V ecosystem

November 30, 2018

Imperas riscvOVPsim brings free, open-source modeling and simulation to RISC-V ecosystem

Imperas Software has released the RISC-V Open Virtual Platform Simulator (riscvOVPsim), a free simulator and open-source model of a single-core RISC-V CPU.

OXFORD, ENGLAND. Imperas Software has released the RISC-V Open Virtual Platform Simulator (riscvOVPsim), a free simulator and open-source model of a single-core RISC-V CPU. riscvOVPsim acts as a reference instruction set simulator that delivers high-level simulation for development and compliance testing, allowing RISC-V software engineers to begin development before the availability of silicon and hardware engineers to accelerate design verification.

The open-source model in riscvOVPsim is a Fast Processor Model of current 32/64-bit RISC-V instruction set feature specifications that can be configured to any single-core RISC-V CPU variant. The model covers RISC-V User and Privilege specifications, and can be used as a platform target for developing bare metal applications.

riscvOVPsim includes an instruction-accurate simulator based on Imperas OVP technology for use in compliance and test development. The simulator runs over 1 billion instructions per second on a standard hose PC, and includes configurable runtime settings for all RISC-V specification options.

To download the free and open-source riscvOVPsim, visit the OVP Simulator for RISC-V GitHub repository.

For more information on riscvOVPsim, watch Simon Davidmann, CEO of Imperas Technology, review the technology below.

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