Excitation current mismatch effects in three-wire RTD measurement systems, Part 3
March 30, 2015
In Part 1 and Part 2 we discussed the benefits of constructing a ratiometric three-wire resistance temperature detectors (RTD) system along with an er...
In Part 1 and Part 2 we discussed the benefits of constructing a ratiometric three-wire resistance temperature detectors (RTD) system along with an error analysis of an example integrated circuit (IC) implementation. We showed that while a ratiometric RTD configuration removes the errors from the initial accuracy of the excitation currents, mismatch and mismatch drift between the two excitation currents still causes gain error. In most circuits, including integrated solutions, the excitation current mismatch is the largest error source. Additionally, the excitation current mismatch temperature drift is the largest over-temperature error.
In Part 3 we discuss two ways to remove the effects of the excitation current mismatch and mismatch drift. The first method is a software approach using the multiplexer internal to most integrated solutions. The second method is a hardware approach that modifies the circuit topology.
Chopping the excitation current sources
One technique used to reduce errors from the excitation current mismatch is to alternate the routing of the currents between the inputs. This is commonly known as “chopping.” The excitation currents are injected into the RTD circuit and then swapped while taking a reading at each setting. The average value of the two readings will not be affected by the mismatch between the two excitation currents. In the most integrated solutions, this can be realized using the built-in multiplexer to alternate the routing of the excitation currents to the two outputs. Figure 1 illustrates how the excitation currents are chopped in the circuit we analyzed in Part 2.
When the excitation currents are swapped, the system designer must wait until the input signal has settled in order to take a valid measurement. Settling time is based on the selected analog-to-digital converter (ADC), as well as any external filtering that has been implemented. Switching the multiplexer and waiting to take readings adds delay to the measurement system and may be undesirable in some applications. As timing becomes more complex, so do the digital processing algorithms required to convert the average results into a temperature reading.
Three-wire RTD measurement system with high-side reference
A more effective alternative to chopping the excitation currents is to place the reference resistor on the high-side of the RTD sensor (Figure 2). In this configuration, only one excitation current flows through both the reference resistor and RTD. The second excitation current is used only for the three-wire RTD lead-resistance cancellation. Because only one excitation current creates the reference and input voltages, the current source mismatch and mismatch drift will no longer affect the ADC transfer function. Any mismatch error only impacts the effectiveness of the RTD lead cancellation, which is no different than the original circuit.
High-side reference circuit configuration
The new configuration poses some additional design challenges by moving the low-side reference resistor to the high side of the RTD. First, an additional resistor, RBIAS, must be connected from the RTD to ground. The voltage across RBIAS, VBIAS, shifts the RTD voltage within the ADC’s linear input common-mode voltage range. This must be done while keeping the voltage at the current output digital-to-analog converter (IDAC) outputs below their compliance voltage rating.
The input common-mode voltage, VCM, for the circuit in Figure 2 is defined in Equation (1).
The input common-mode voltage for the programmable gain amplifier (PGA) must be kept within the range outlined in the product datasheet. Equation (2) shows two limits for the minimum common-mode voltage, VCM MIN. Use the larger of these two values for VCM MIN. Equation (3) defines the maximum common-mode voltage, VCM MAX.
The voltage at the IDAC output cannot exceed the compliance voltage or they will not function properly. The IDAC compliance voltage is defined in Equation (4).
In this circuit configuration, the largest IDAC output voltage is at IDAC1, VIDAC1 MAX. The voltage at VIDAC1 is calculated in Equation (5).
Based on the same +3.3 V supply used in Part 2, the values for the minimum and maximum common-mode voltages, along with the IDAC compliance voltage, are shown in Table 1.
In the high-side reference configuration, voltage at the IDAC outputs increases because RBIAS is added, which decreases the amount of available headroom. In order to meet the IDAC voltage compliance, the reference or bias voltage may need to be reduced by adjusting the IDAC current or the resistor values. In turn, a different IDAC current may require an adjustment in PGA gain to maintain system resolution.
Satisfying the input common-mode and IDAC compliance voltage limits is still practical with the proposed high-side reference solution. First, select the bias voltage such that it exceeds VCM MIN. This maximizes headroom for the IDAC compliance voltage requirement. Then, based on the maximum RTD voltage, select a reference voltage and PGA gain setting to maximize system resolution.
Table 2 lists the circuit values for a properly optimized high-side reference circuit with a +3.3V supply. The VCM MIN and VCM MAX voltages in the circuit, along with the VIDAC1 MAX voltage, are also listed. Notice that the max ADC input voltage utilizes most of the VREF voltage range while being sure not to violate the common-mode and IDAC compliance limits listed in Table 1.
High-side reference circuit total error
We analyzed the errors contributed by the ADC and RREF using the same method described in Part 2. Although the equations and error sources remain the same, the input-referred voltage errors will change, based on the newly selected IDAC current and component values in the circuit. Table 3 summarizes the error sources and calculates the probable total error for the high-side reference circuit at 25 °C. As shown, the error from the IDAC mismatch is removed. Total error is calculated using Equation (6).
The total input-referred voltage error, once again, can be converted to temperature error.
Removing the excitation current mismatch error results in a 67 percent reduction in the uncalibrated temperature error, compared to the 1.589 °C error calculated in the original low-side reference configuration.
High-side reference circuit drift error
Table 4 lists the ADS1220 temperature drift errors for a TA = -40 °C to +85 °C system operating temperature range. As shown, errors due to the IDAC mismatch drift are also eliminated using the high-side reference configuration.
Eliminating the errors due to the IDAC mismatch reduces the input-referred drift errors from 119.6 µV to only 18.2 µV. The total drift error now accounts for only an additional ±0.062 °C of temperature error over the -40 °C to 85 °C, versus the ±0.306 °C from the low-side reference circuit. Eliminating errors from the excitation current mismatch may reduce the need for, or the requirements of, over-temperature calibration.
The excitation current mismatch is commonly the largest error source, both at room and over temperatures in standard ratiometric three-wire RTD measurement circuits. Chopping the excitation currents is a simple way to reduce the effects of excitation current mismatch in a traditional low-side reference ratiometric RTD acquisition circuit. However, modifying the circuit to a high-side reference configuration eliminates the effects of the excitation current mismatch and mismatch drift while introducing zero measurement delay and minimal additional components. The high-side configuration can be used for low supply voltages, as long as the input common-mode voltage and excitation current compliance voltage limits are abided.
In Part 1 we discussed the principles behind standard three-wire ratiometric RTD acquisition circuits and explained that the mismatch of the two excitation currents causes a gain error in the acquisition circuit. In Part 2 we applied the theory from Part 1 to a real RTD acquisition circuit to display the effects of the excitation current mismatch compared to other design errors. The excitation current mismatch was found to be the largest error, both at 25 °C and over temperature due to mismatch drift. In Part 3 we featured two solutions to reduce or eliminate the errors from the IDAC mismatch. We showed how to reconfigure the circuit to a high-side reference circuit to completely eliminate the effects of the excitation current mismatch and mismatch drift with only one additional component.