eSilicon Completes Tapeout of 7nm 400G Gearbox/Retimer Test ASIC

May 03, 2019

eSilicon Completes Tapeout of 7nm 400G Gearbox/Retimer Test ASIC

The test ASIC includes x4 112 Gbps SerDes and x8 56 Gbps SerDes, which are integrated with media access control, forward error correction, and gearbox E-pak Ethernet IP from Precise-ITC.

SAN JOSE, CA. eSilicon has completed the tapeout of a 7 nm test ASIC that supports 400G gearbox and retimer functionality. The test ASIC includes x4 112 Gbps SerDes and x8 56 Gbps SerDes, which are integrated with media access control, forward error correction, and gearbox E-pak Ethernet IP from Precise-ITC. Technology in the chip will provide the foundation for developing 400G and 800G systems.

A gearbox converts multiple serial data streams at one rate to streams at another rate, while a retimer improves signal integrity by equalizing, retiming, and reconditioning received signals so that their range can be extended. eSilicon’s StarDesigner 7 nm flow was used in the design of the test ASIC to help meet stringent performance parameters, including long reach, low power, and low latency.

The test ASIC will be out of fabrication in September 2019, at which point eSilicon will release measurement and availability information.

The 7nm gearbox/retimer test ASIC will be out of fabrication in September, 2019. eSilicon will announce silicon measurement data and availability at that time.

For more information on eSilicon’s 7 nm IP, visit www.esilicon.com/products/technologies/finfet-class-7nm-ip-platform.

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