Embedded DisplayPort: Increased flexibility and power savings render greater display efficiency
December 01, 2012
While mobile device display performance continues to increase, system chip processes geometries continue to shrink, resulting in a greater proportion...
The Video Electronics Standards Association (VESA) first released the Embedded DisplayPort (eDP) standard in 2009 as an extension of the DisplayPort standard for use with embedded displays. VESA developed eDP to replace the aging Low-Voltage Differential Signaling (LVDS) standard, and today eDP is used widely in notebook computers and all-in-one systems. The primary benefits of eDP over LVDS include the reduction of signal wires due to its higher data rate, compatibility with submicron chip processes, decreased interference with wireless services, and its ability to accommodate new features.
Since its initial release the eDP standard has gone through a series of revisions adding new features not shared with DisplayPort, as eDP has evolved to target battery-operated embedded display systems. For example, in 2010 eDP version 1.2 was published, adding control of display and backlight features over the auxiliary channel. In 2011 eDP version 1.3 introduced Panel Self Refresh (PSR).
While eDP was originally designed for notebooks and all-in-one systems, it is becoming increasingly optimized for smaller form factor systems including tablet and PC smart phone applications. Released in December 2012, eDP version 1.4 adds new optional features developed to address this broader range of form factors and further reduce system power.
The importance of lowering display-related system power
Today, mobile devices are a major driving force in the electronics industry. Every year new mobile devices are introduced with increased processing capability, better displays, a smaller and lighter form factor, and extended battery life. Taking into account typical CPU idle time, an average display consumes about 75 percent of system power. While system chip power reduction is accomplished through shrinking semiconductor process geometries, display power reduction comes through improvements in backlight and LCD technologies, as well as new pixel structures.
However, the recent trend toward brighter, higher-resolution displays is driving up display power. The second-generation iPad had a 1024x768 display and a 25 watt-hour battery, while the latest iPod has a 2048x1536 display (a 400 percent pixel increase) and a 42.5 watt-hour battery (a 70 percent power increase), both delivering a 10-hour battery life. The higher-resolution display requires additional pixel-driving circuitry and a higher data rate display interface, as well as faster Graphics Processing Unit (GPU) rendering and display image processing circuitry.
This display power challenge has led to many new architectural developments at the platform level. Reducing display power means longer battery life and less battery capacity requirement and therefore smaller, lighter, and less expensive systems. Rather than being treated as a simple rendering device, display deployment has become more integrated into the overall system design. The new eDP v1.4 brings many of these concepts together, as explained in the following discussion.
Panel Self Refresh (PSR)
Introduced in eDP v1.3, the PSR function provides a means to lower display-related system power by allowing portions of the GPU and display interface to enter a low-power state during a static display image condition (see Figure 1). When the system enters PSR mode, the remote frame buffer built into the LCD timing controller (Tcon) performs the routine display refresh task, offloading the GPU and display interface. The local frame buffer can then be updated later by the GPU with a new static image (such as when a flashing cursor is turned on or off), or the system can exit from PSR mode to display constantly changing images (such as when playing a video). Because most displays are refreshed 60 times per second, PSR allows the GPU circuits and display interface to remain in a low-power state for most of the system operating time, resulting in significant power savings.
PSR with selective frame update
The latest version of eDP enhances the PSR mechanisms by enabling updates to selected regions of the video frame in the Tcon frame buffer. With eDP v1.3, the entire frame must be updated every time any portion of the image changes. With eDP v1.4, only the new portion of the frame requires updating (see Figure 2). This lets the GPU display interface remain active for a shorter duration, further reducing system power.
Additional eDP v1.4 features that support PSR
Advanced link power management
The ability to manage the display interface is improved in eDP v1.4 by greatly reducing the wake-up time from the low-power state, which is important to maximize the efficiency of the PSR selective update process. Previous versions of eDP required more than 100 microseconds to wake up and retrain the data link. With eDP v1.4, if the new PSR mode is supported, wake-up from standby is a maximum 0.5 microseconds, and wake time from the lower-power sleep state is 20 microseconds.
Video timing synchronization
In DisplayPort and earlier versions of eDP, display-to-GPU synchronization is performed over the DisplayPort main link, the high-speed data channel that carries video data using special control codes. In eDP v1.4, frame synchronization is also provided over the lower-speed auxiliary channel. This enables quick bursts of eDP main link operation to perform timely selective updates of the remote frame buffer.
Display stream compression
Display interfaces including DisplayPort and earlier versions of eDP send uncompressed pixel data across the display interface. Image compression is traditionally limited to media delivery to the system or for storage. In the interest of further power savings, eDP v1.4 introduces a display stream compression algorithm that reduces the data rate across the display interface. In contrast to typical video or image compression algorithms, the display stream compression algorithm is optimized for high data throughput, low latency, and low gate count and targets low-compression ratios in the 2x to 5x range, depending on the image type. By using a minimum 2x compression ratio configuration, for example, the display interconnect bandwidth can be cut in half, with typically no loss in image content. Display stream compression can also be used when updating a display’s PSR frame buffer, providing further power savings. It can also be used to support display resolutions beyond the uncompressed main link capability.
Regional backlight control
When eDP v1.2 was released in 2010, it introduced the capability to control LCD backlight modulation frequency and brightness through the auxiliary channel, thus eliminating the need for an extra backlight control interface. In eDP v1.4, regional backlight control provides the option to independently set different portions of the display backlight region. This allows the GPU to actively darken selective portions of the display based on display contents, increasing power savings. Up to 15 backlight regions can be controlled with a single auxiliary transaction.
Multitouch over auxiliary channel
Touch-sensitive displays are common in many smaller embedded display systems and will become more prevalent in PCs. The latest version of eDP adds the ability to transport multitouch data from the display to the host through the auxiliary channel. The multitouch data transport uses a framework that is compatible with the USB Human Interface Device specifications. By eliminating the dedicated USB interface commonly used for this purpose, both electrical connections and power are saved.
Reduced differential voltage swing
Prior to eDP v1.4, the standard utilized the same interface signal voltage amplitudes as DisplayPort. Today, eDP v1.4 reduces the main link’s minimum differential voltage amplitude levels from 400 mV to 200 mV, which is suitable for the short transmission distances in small embedded form factors. This reduces interface drive power by as much as 75 percent, as power is proportional to the square of amplitude. Additional flexibility is also added to the link training amplitude step sizes, helping increase suitability for different transmission media including chip-on-glass.
Increased link rate flexibility
Another addition in eDP v1.4 is greater flexibility in the main link data rate. Previous versions of eDP limited link rate selection to 1.62 Gbps, 2.7 Gbps, and 5.4 Gbps per lane (main link data channel), which is the same as DisplayPort. The current version of eDP now includes seven standard rates, enabling further power efficiency.
With DisplayPort, increasing a 1080p 60 Hz display format from 24-bit color to 30-bit color would require changing a two-lane 2.7 Gbps configuration to either a four-lane 2.7 Gbps configuration or a two-lane 5.4 Gbps configuration. Ether case represents a 100 percent increase in interface bandwidth and power, with only a 25 percent increase in data content (additional dummy bits would be added to make up the difference). With eDP v1.4 in the same application, the rate could be bumped up from 2.7 Gbps to 3.24 Gbps, resulting in only a 20 percent link rate increase.
Customizable link rates are also supported, with a new set of registers defined for the display to declare this capability, as well as the custom link rate frequency. In addition to further power optimization, this increases application diversity as link rates can be adjusted based on particular system timing requirements. It also enables link rate adjustment to mitigate radio frequency interference with system wireless services.
System deployment with eDP v1.4
Offering increased flexibility and reduced system power, the latest release of eDP v1.4 will help propel eDP into new applications and establish it as a universal embedded display interface. Given the current cycle of eDP standard publication and adoption, it is expected that systems using some of the new features in eDP v1.4 will appear on the market in two to three years. Higher-resolution notebook PCs and tablets will likely be the first candidates to leverage this power-optimized interface.