Breker Verification Systems adds Unique Deployment Flows to Trek5 Test Suite Synthesis for UVM Block, Software-Driven SoC
February 19, 2019
Trek5 Shipping in Volume Production to Chip Design Verification Groups Worldwide
Breker Verification Systems, the leading provider of Portable Stimulus Standard (PSS)-compliant software, today began full-volume production of Trek5™ that includes a feature-rich set of expanded capabilities in addition to Portable Stimulus test suite synthesis.
In addition to classic PSS model solving, Trek5’s Test Suite Synthesis new capabilities allow tests to be optimized for universal verification methodology (UVM) block verification, Software-Driven Verification (SDV) and Post-Silicon environments. Its unique TrekDebug tool enables post-verification debug, profiling and coverage.
“Breker often gets tagged as ‘one of the Portable Stimulus tool vendors,’” asserts Adnan Hamid, Breker’s CEO and founder. “Trek5 sets us apart and validates our position to offer complete solutions across the verification spectrum, of which Portable Stimulus synthesis is just the first step. Other vendors focus on simply solving PSS models to basic tests with plenty of hand coding for environment integration. Breker built its formidable reputation by automating this process and simplifying UVM test authoring for complex blocks, enabling powerful SDV test sets complete with comprehensive system services to drive test portability through to post-silicon.”
The Trek5 Difference
The Trek5 tool suite includes TrekGen™ for PSS-based test suite synthesis, TrekUVM™, TrekSoC™ and TrekSoC-Si™ deployment optimizers, TrekDebug™ for post-verification analysis, the TrekDesigner™ graphical entry tool and a range of TrekApps™.
TrekGen, a fully functional and compliant Portable Stimulus synthesis tool generates tests from both the Domain Specific Language (DSL) and C++ variants of the Accellera PSS using advanced solvers. It allows path constraints and path coverage to be applied across standard scenario models and includes advanced procedural support for power users. TrekDesigner, a graphical entry tool, together with a full range of pre-verification analysis capabilities for reachability, coverage and test inspection, comes with TrekGen.
In addition to TrekGen, a distinct range of deployment optimizers for three flows –– UVM, SDV and post-silicon –– further differentiates Trek5. Designed to be portable across flows, they allow Portable Stimulus-generated tests to be deployed directly into existing test environments with minimal additional effort.
These features alleviate the need for end users to write excessive SystemVerilog and C code into their PSS models to generate testbench code.
TrekUVM optimizes complex sequences, coverage and scoreboards using test scheduling synthesis and other capabilities for existing UVM environments. Particularly appropriate for larger blocks with multiple I/O ports, TrekUVM allows multi-threaded, synchronized sequence streams to be generated from a single, easy-to-understand, white-box scenario specification.
TrekSoC includes a Hardware/Software Interface (HSI) that affords micro-kernel OS-like services to simplify bare-metal processor C tests. Also included are advanced memory allocation testing, TrekBox backdoor memory access and other capabilities. This enables multi-threaded processor C tests and I/O transactions to be transparently generated for system-on-chip (SoC) designs without end-user integration effort. Simulation and emulation variants are included.
Diagnostic tests are supplied by TrekSoC-Si for post-fabricated silicon or field programmable gate array (FPGA) prototyping systems that make use of the same verification scenario tests. TrekSoC-Si includes hardware access so that the same environment can be used as with the Trek verification solutions, providing visibility and simplifying test monitoring and analysis.
TrekDebug, another unique tool from Breker, allows self-checking, multi-threaded tests to be monitored and debugged, along with full coverage analysis and design profiling and optimization. This solution accesses common signal-level debuggers, such as Synopsys’ Verdi, to accelerate the debug process.
Finally, TrekApps provide solutions to common verification tasks, including cache coherency, ARMv8 installation testing and power-management analysis with more to follow. They deliver fully configurable test environments without the need to understand the PSS languages.
The entire Trek5 portfolio will be demonstrated in the Breker booth (#701) during DVCon Monday, February 25, through Wednesday, February 27, at the DoubleTree Hotel in San Jose, Calif.
Breker will co-sponsor the Verification 3.0 Innovation Summit Tuesday, March 19, at the Levi Stadium Conference Center in Santa Clara, Calif. More details will be available soon.
Availability and Pricing
Trek5 is in full-volume production now. Pricing is available upon request.
To learn more, visit www.brekersystems.com
About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from abstract scenario models. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across the verification process, and Shareable to foster team communication and reuse. Breker’s Intelligent Testbench suite of tools and apps allows the synthesis of high-coverage, powerful test cases for deployment into a variety of UVM to SoC verification environments. Breker is privately held, and works with leading semiconductor companies worldwide.
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